From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Gibson Subject: Re: [PATCH v3 10/17] KVM: PPC: Book3S HV: XIVE: add get/set accessors for the VP XIVE state Date: Tue, 19 Mar 2019 16:08:22 +1100 Message-ID: <20190319050821.GC31018@umbus.fritz.box> References: <20190315120609.25910-1-clg@kaod.org> <20190315120609.25910-11-clg@kaod.org> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="f0KYrhQ4vYSV2aJu" Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org To: =?iso-8859-1?Q?C=E9dric?= Le Goater Return-path: Content-Disposition: inline In-Reply-To: <20190315120609.25910-11-clg@kaod.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@lists.ozlabs.org Sender: "Linuxppc-dev" List-Id: kvm.vger.kernel.org --f0KYrhQ4vYSV2aJu Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 15, 2019 at 01:06:02PM +0100, C=E9dric Le Goater wrote: > The state of the thread interrupt management registers needs to be > collected for migration. These registers are cached under the > 'xive_saved_state.w01' field of the VCPU when the VPCU context is > pulled from the HW thread. An OPAL call retrieves the backup of the > IPB register in the underlying XIVE NVT structure and merges it in the > KVM state. >=20 > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson [snip] > diff --git a/Documentation/virtual/kvm/devices/xive.txt b/Documentation/v= irtual/kvm/devices/xive.txt > index e6a984592189..eb864d72ddc3 100644 > --- a/Documentation/virtual/kvm/devices/xive.txt > +++ b/Documentation/virtual/kvm/devices/xive.txt > @@ -104,6 +104,25 @@ the legacy interrupt mode, referred as XICS (POWER7/= 8). > -ENOENT: Unknown source number > -EINVAL: Not initialized source number > =20 > +* VCPU state > + > + The XIVE IC maintains VP interrupt state in an internal structure > + called the NVT. When a VP is not dispatched on a HW processor > + thread, this structure can be updated by HW if the VP is the target > + of an event notification. > + > + It is important for migration to capture the cached IPB from the NVT > + as it synthesizes the priorities of the pending interrupts. We > + capture a bit more to report debug information. > + > + KVM_REG_PPC_VP_STATE (4 * 64bits) > + bits: | 63 .... 32 | 31 .... 0 | > + values: | TIMA word0 | TIMA word1 | > + bits: | 127 .......... 64 | > + values: | unused | > + bits: | 255 .......... 128 | > + values: | unused | > + > * Migration: > =20 > Saving the state of a VM using the XIVE native exploitation mode Nit: looks like this doc needs to be updated now that only 2x 64-bit values are returned. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --f0KYrhQ4vYSV2aJu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlyQeUMACgkQbDjKyiDZ s5IPnQ//Yw6FUlp92I+KVwVQGNHQt7mtHGrQUbkp8mcU6fn9v5iXp8YWWrooyh7g Bt46WJb/uDDuG3y5myNLURC/PPzhQ6LxZ6KZKsQOWIOg73dc6dDwwaedikHYr092 wLMg3lix5fEuxkFhC17zo5n2P/K1ciwUsrhL7KjqsoS4V7pcrS2fukZ017+jMAU+ 6mGGGT3diN84hWsz/OwfgUQSyJuxVzjz2Y0OB0by6mjlrgq+x+7WVEtyJYVDHWTx Ayeu6szg6CqaDSZj0QRUQ5bOGLM9/64MqmePFPX3ZQRZA2jdBVUGPoEqeg3y0xeI 6a5pmnD8j0xZLpsdiuv3hq+FuuKuFFHGtqO8MAMa80UAetRrD24kUcpWjin2p6WY mEQgDmmwFPVzVuXeVqH/InaETlGrL+qzjsd1OjT64L153uRNtVP/M8ZVnIbG3yqV Tn5XDXgGV4FIbd1kD5b2Ivhy3O+Dn/LdCwB8ptc8xK4WIpY9REgr6A3Y7H3naUZ3 GlDjJElY98Kkn3bN6Ae2YEd7G4xIhDMNzNp53rjPgHVU3t9FT3wAkns5e3ZRr4N3 bWYpeaeKnw/TWKJkFgwwI9oZRwzxwqE9rD/wyutfY3FAjPMSLhNi56Ie5h5qyHQe KOmwhXTldaLaDUJWbQijtqrA1jxIEGd82Ph/YclmVex3xT2s/20= =u344 -----END PGP SIGNATURE----- --f0KYrhQ4vYSV2aJu-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Gibson Date: Tue, 19 Mar 2019 05:08:22 +0000 Subject: Re: [PATCH v3 10/17] KVM: PPC: Book3S HV: XIVE: add get/set accessors for the VP XIVE state Message-Id: <20190319050821.GC31018@umbus.fritz.box> MIME-Version: 1 Content-Type: multipart/mixed; boundary="f0KYrhQ4vYSV2aJu" List-Id: References: <20190315120609.25910-1-clg@kaod.org> <20190315120609.25910-11-clg@kaod.org> In-Reply-To: <20190315120609.25910-11-clg@kaod.org> To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org --f0KYrhQ4vYSV2aJu Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 15, 2019 at 01:06:02PM +0100, C=E9dric Le Goater wrote: > The state of the thread interrupt management registers needs to be > collected for migration. These registers are cached under the > 'xive_saved_state.w01' field of the VCPU when the VPCU context is > pulled from the HW thread. An OPAL call retrieves the backup of the > IPB register in the underlying XIVE NVT structure and merges it in the > KVM state. >=20 > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson [snip] > diff --git a/Documentation/virtual/kvm/devices/xive.txt b/Documentation/v= irtual/kvm/devices/xive.txt > index e6a984592189..eb864d72ddc3 100644 > --- a/Documentation/virtual/kvm/devices/xive.txt > +++ b/Documentation/virtual/kvm/devices/xive.txt > @@ -104,6 +104,25 @@ the legacy interrupt mode, referred as XICS (POWER7/= 8). > -ENOENT: Unknown source number > -EINVAL: Not initialized source number > =20 > +* VCPU state > + > + The XIVE IC maintains VP interrupt state in an internal structure > + called the NVT. When a VP is not dispatched on a HW processor > + thread, this structure can be updated by HW if the VP is the target > + of an event notification. > + > + It is important for migration to capture the cached IPB from the NVT > + as it synthesizes the priorities of the pending interrupts. We > + capture a bit more to report debug information. > + > + KVM_REG_PPC_VP_STATE (4 * 64bits) > + bits: | 63 .... 32 | 31 .... 0 | > + values: | TIMA word0 | TIMA word1 | > + bits: | 127 .......... 64 | > + values: | unused | > + bits: | 255 .......... 128 | > + values: | unused | > + > * Migration: > =20 > Saving the state of a VM using the XIVE native exploitation mode Nit: looks like this doc needs to be updated now that only 2x 64-bit values are returned. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --f0KYrhQ4vYSV2aJu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlyQeUMACgkQbDjKyiDZ s5IPnQ//Yw6FUlp92I+KVwVQGNHQt7mtHGrQUbkp8mcU6fn9v5iXp8YWWrooyh7g Bt46WJb/uDDuG3y5myNLURC/PPzhQ6LxZ6KZKsQOWIOg73dc6dDwwaedikHYr092 wLMg3lix5fEuxkFhC17zo5n2P/K1ciwUsrhL7KjqsoS4V7pcrS2fukZ017+jMAU+ 6mGGGT3diN84hWsz/OwfgUQSyJuxVzjz2Y0OB0by6mjlrgq+x+7WVEtyJYVDHWTx Ayeu6szg6CqaDSZj0QRUQ5bOGLM9/64MqmePFPX3ZQRZA2jdBVUGPoEqeg3y0xeI 6a5pmnD8j0xZLpsdiuv3hq+FuuKuFFHGtqO8MAMa80UAetRrD24kUcpWjin2p6WY mEQgDmmwFPVzVuXeVqH/InaETlGrL+qzjsd1OjT64L153uRNtVP/M8ZVnIbG3yqV Tn5XDXgGV4FIbd1kD5b2Ivhy3O+Dn/LdCwB8ptc8xK4WIpY9REgr6A3Y7H3naUZ3 GlDjJElY98Kkn3bN6Ae2YEd7G4xIhDMNzNp53rjPgHVU3t9FT3wAkns5e3ZRr4N3 bWYpeaeKnw/TWKJkFgwwI9oZRwzxwqE9rD/wyutfY3FAjPMSLhNi56Ie5h5qyHQe KOmwhXTldaLaDUJWbQijtqrA1jxIEGd82Ph/YclmVex3xT2s/20= =u344 -----END PGP SIGNATURE----- --f0KYrhQ4vYSV2aJu--