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From: Andes <uboot@andestech.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.
Date: Tue, 19 Mar 2019 17:07:49 +0800	[thread overview]
Message-ID: <20190319090750.8923-9-uboot@andestech.com> (raw)
In-Reply-To: <20190319090750.8923-1-uboot@andestech.com>

From: Rick Chen <rick@andestech.com>

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
---
 arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++++++++------------
 arch/riscv/dts/ae350_64.dts | 47 +++++++++++++++++++++++---
 2 files changed, 101 insertions(+), 27 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..0b4d966 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -25,17 +25,50 @@
 			reg = <0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv32imafdc";
+			riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
 			mmu-type = "riscv,sv32";
 			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 			CPU0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
 				compatible = "riscv,cpu-intc";
 			};
 		};
+		CPU1: cpu at 1 {
+		device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		L2: l2-cache at e0500000 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <0x40000>;
+			reg = <0x0 0xe0500000 0x0 0x40000>;
+		};
 	};
 
 	memory at 0 {
@@ -49,29 +82,29 @@
 		compatible = "andestech,riscv-ae350-soc";
 		ranges;
 
-	plic0: interrupt-controller at e4000000 {
-		compatible = "riscv,plic0";
-		#address-cells = <1>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		reg = <0xe4000000 0x2000000>;
-		riscv,ndev=<71>;
-		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-	};
+		plic0: interrupt-controller at e4000000 {
+			compatible = "riscv,plic0";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe4000000 0x2000000>;
+			riscv,ndev=<71>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
+		};
 
-	plic1: interrupt-controller at e6400000 {
-		compatible = "riscv,plic1";
-		#address-cells = <1>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		reg = <0xe6400000 0x400000>;
-		riscv,ndev=<1>;
-		interrupts-extended = <&CPU0_intc 3>;
-	};
+		plic1: interrupt-controller at e6400000 {
+			compatible = "riscv,plic1";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe6400000 0x400000>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
+		};
 
-	plmt0 at e6000000 {
-		compatible = "riscv,plmt0";
-			interrupts-extended = <&CPU0_intc 7>;
+		plmt0 at e6000000 {
+			compatible = "riscv,plmt0";
+			interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
 			reg = <0xe6000000 0x100000>;
 		};
 	};
@@ -146,6 +179,10 @@
 		interrupt-parent = <&plic0>;
 	};
 
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
 	virtio_mmio at fe007000 {
 		interrupts = <0x17 0x4>;
 		interrupt-parent = <0x2>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index e48c298..3c7e152 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -25,17 +25,50 @@
 			reg = <0>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
+			riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
 			mmu-type = "riscv,sv39";
 			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 			CPU0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
 				compatible = "riscv,cpu-intc";
 			};
 		};
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		L2: l2-cache at e0500000 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-size = <0x40000>;
+			reg = <0x0 0xe0500000 0x0 0x40000>;
+		};
 	};
 
 	memory at 0 {
@@ -56,7 +89,7 @@
 		interrupt-controller;
 		reg = <0x0 0xe4000000 0x0 0x2000000>;
 		riscv,ndev=<71>;
-		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
 	};
 
 	plic1: interrupt-controller at e6400000 {
@@ -65,13 +98,13 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0x0 0xe6400000 0x0 0x400000>;
-		riscv,ndev=<1>;
-		interrupts-extended = <&CPU0_intc 3>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
 	};
 
 	plmt0 at e6000000 {
 		compatible = "riscv,plmt0";
-			interrupts-extended = <&CPU0_intc 7>;
+      interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
 			reg = <0x0 0xe6000000 0x0 0x100000>;
 		};
 	};
@@ -146,6 +179,10 @@
 		interrupt-parent = <&plic0>;
 	};
 
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
 	virtio_mmio at fe007000 {
 		interrupts = <0x17 0x4>;
 		interrupt-parent = <0x2>;
-- 
2.7.4

  parent reply	other threads:[~2019-03-19  9:07 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-19  9:07 [U-Boot] [PATCH 0/9] AE350 SMP support RISC-V Andes
2019-03-19  9:07 ` [U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node Andes
2019-03-20  7:22   ` Bin Meng
2019-03-21  6:49     ` Rick Chen
2019-03-21  7:01       ` Bin Meng
2019-03-21  8:28         ` Rick Chen
2019-03-21  8:49           ` Bin Meng
2019-03-21  9:01             ` Rick Chen
2019-03-21  9:16               ` Bin Meng
2019-04-10  9:05                 ` Rick Chen
2019-04-10  9:21                   ` Auer, Lukas
2019-04-10  9:30                     ` Rick Chen
2019-03-19  9:07 ` [U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC Andes
2019-03-20  7:22   ` Bin Meng
2019-03-21  7:04     ` Rick Chen
2019-03-21  7:32       ` Bin Meng
2019-03-21  8:39         ` Rick Chen
2019-03-21 16:24           ` Troy Benjegerdes
2019-03-19  9:07 ` [U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT Andes
2019-03-20  7:22   ` Bin Meng
2019-03-21  8:41     ` Rick Chen
2019-03-19  9:07 ` [U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC Andes
2019-03-19  9:07 ` [U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer Andes
2019-03-20  7:22   ` Bin Meng
2019-03-19  9:07 ` [U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options Andes
2019-03-20  7:22   ` Bin Meng
2019-03-19  9:07 ` [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode Andes
2019-03-20  7:22   ` Bin Meng
2019-03-21  8:42     ` Rick Chen
2019-03-19  9:07 ` Andes [this message]
2019-03-20  7:22   ` [U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP Bin Meng
2019-03-21  8:51     ` Rick Chen
2019-03-21  9:15       ` Bin Meng
2019-03-21  9:38         ` Rick Chen
2019-03-21 10:12           ` Bin Meng
2019-03-21 10:16             ` Rick Chen
2019-03-19  9:07 ` [U-Boot] [PATCH 9/9] riscv: ae350: enable SMP Andes
2019-03-20  7:22   ` Bin Meng

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