* [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
@ 2019-03-21 18:01 José Roberto de Souza
2019-03-21 18:01 ` [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct José Roberto de Souza
` (11 more replies)
0 siblings, 12 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
PSR is only support in eDP transcoder and there is only one instance
of it, so lets drop all of this code.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 17 +---
drivers/gpu/drm/i915/intel_psr.c | 147 ++++++++-----------------------
2 files changed, 42 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b46910453e61..d0ca6ef6d630 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4277,13 +4277,9 @@ enum {
/* Bspec claims those aren't shifted but stay at 0x64800 */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
-#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
-#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
-#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
-#define EDP_PSR_TRANSCODER_C_SHIFT 24
-#define EDP_PSR_TRANSCODER_B_SHIFT 16
-#define EDP_PSR_TRANSCODER_A_SHIFT 8
-#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
+#define EDP_PSR_ERROR (1 << 2)
+#define EDP_PSR_POST_EXIT (1 << 1)
+#define EDP_PSR_PRE_ENTRY (1 << 0)
#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
@@ -4348,12 +4344,7 @@ enum {
#define EDP_PSR2_IDLE_FRAME_MASK 0xf
#define EDP_PSR2_IDLE_FRAME_SHIFT 0
-#define _PSR_EVENT_TRANS_A 0x60848
-#define _PSR_EVENT_TRANS_B 0x61848
-#define _PSR_EVENT_TRANS_C 0x62848
-#define _PSR_EVENT_TRANS_D 0x63848
-#define _PSR_EVENT_TRANS_EDP 0x6F848
-#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
+#define PSR_EVENT _MMIO(0x6F848)
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
#define PSR_EVENT_PSR2_DISABLED (1 << 16)
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 605fe8fc85cc..dc9fdb515a54 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -84,46 +84,12 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
-{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
-
void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
+ u32 mask = EDP_PSR_ERROR;
if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
+ mask |= EDP_PSR_POST_EXIT | EDP_PSR_PRE_ENTRY;
I915_WRITE(EDP_PSR_IMR, ~mask);
}
@@ -167,62 +133,47 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
- ktime_t time_ns = ktime_get();
- u32 mask = 0;
+ ktime_t time_ns = ktime_get();
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
- transcoder_name(cpu_transcoder));
-
- dev_priv->psr.irq_aux_error = true;
-
- /*
- * If this interruption is not masked it will keep
- * interrupting so fast that it prevents the scheduled
- * work to run.
- * Also after a PSR error, we don't want to arm PSR
- * again so we don't care about unmask the interruption
- * or unset irq_aux_error.
- */
- mask |= EDP_PSR_ERROR(shift);
- }
+ if (psr_iir & EDP_PSR_ERROR) {
+ u32 mask;
- if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
- dev_priv->psr.last_entry_attempt = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
- transcoder_name(cpu_transcoder));
- }
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+ transcoder_name(TRANSCODER_EDP));
- if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
- dev_priv->psr.last_exit = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
- transcoder_name(cpu_transcoder));
+ dev_priv->psr.irq_aux_error = true;
- if (INTEL_GEN(dev_priv) >= 9) {
- u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
- bool psr2_enabled = dev_priv->psr.psr2_enabled;
+ /*
+ * If this interruption is not masked it will keep
+ * interrupting so fast that it prevents the scheduled
+ * work to run.
+ * Also after a PSR error, we don't want to arm PSR
+ * again so we don't care about unmask the interruption
+ * or unset irq_aux_error.
+ */
+ mask = I915_READ(EDP_PSR_IMR) | EDP_PSR_ERROR;
+ I915_WRITE(EDP_PSR_IMR, mask);
- I915_WRITE(PSR_EVENT(cpu_transcoder), val);
- psr_event_print(val, psr2_enabled);
- }
- }
+ schedule_work(&dev_priv->psr.work);
}
- if (mask) {
- mask |= I915_READ(EDP_PSR_IMR);
- I915_WRITE(EDP_PSR_IMR, mask);
+ if (psr_iir & EDP_PSR_PRE_ENTRY) {
+ dev_priv->psr.last_entry_attempt = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
+ transcoder_name(TRANSCODER_EDP));
+ }
- schedule_work(&dev_priv->psr.work);
+ if (psr_iir & EDP_PSR_POST_EXIT) {
+ DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
+ transcoder_name(TRANSCODER_EDP));
+
+ if (INTEL_GEN(dev_priv) >= 9) {
+ u32 val = I915_READ(PSR_EVENT);
+ bool psr2_enabled = dev_priv->psr.psr2_enabled;
+
+ I915_WRITE(PSR_EVENT, val);
+ psr_event_print(val, psr2_enabled);
+ }
}
}
@@ -672,30 +623,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
dev_priv->psr.active = true;
}
-static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
- enum transcoder cpu_transcoder)
-{
- static const i915_reg_t regs[] = {
- [TRANSCODER_A] = CHICKEN_TRANS_A,
- [TRANSCODER_B] = CHICKEN_TRANS_B,
- [TRANSCODER_C] = CHICKEN_TRANS_C,
- [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
- };
-
- WARN_ON(INTEL_GEN(dev_priv) < 9);
-
- if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
- !regs[cpu_transcoder].reg))
- cpu_transcoder = TRANSCODER_A;
-
- return regs[cpu_transcoder];
-}
-
static void intel_psr_enable_source(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 mask;
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
@@ -706,13 +637,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv))) {
- i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
- cpu_transcoder);
- u32 chicken = I915_READ(reg);
+ u32 chicken = I915_READ(CHICKEN_TRANS_EDP);
chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
PSR2_ADD_VERTICAL_LINE_COUNT;
- I915_WRITE(reg, chicken);
+ I915_WRITE(CHICKEN_TRANS_EDP, chicken);
}
/*
@@ -1225,7 +1154,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
* to avoid any rendering problems.
*/
val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP));
+ val &= EDP_PSR_ERROR;
if (val) {
DRM_DEBUG_KMS("PSR interruption error set\n");
dev_priv->psr.sink_not_reliable = true;
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:01 ` [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base José Roberto de Souza
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
Lets keep all PSR variables packed in this struct.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
drivers/gpu/drm/i915/intel_psr.c | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6d674aa2786..5f60ad4d4296 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -496,6 +496,7 @@ struct i915_drrs {
};
struct i915_psr {
+ u32 mmio_base;
struct mutex lock;
#define I915_PSR_DEBUG_MODE_MASK 0x0f
@@ -1535,8 +1536,6 @@ struct drm_i915_private {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
- u32 psr_mmio_base;
-
u32 pps_mmio_base;
wait_queue_head_t gmbus_wait_queue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0ca6ef6d630..28728399e607 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4248,7 +4248,7 @@ enum {
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64800
#define BDW_EDP_PSR_BASE 0x6f800
-#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
+#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0)
#define EDP_PSR_ENABLE (1 << 31)
#define BDW_PSR_SINGLE_FRAME (1 << 30)
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
@@ -4281,16 +4281,16 @@ enum {
#define EDP_PSR_POST_EXIT (1 << 1)
#define EDP_PSR_PRE_ENTRY (1 << 0)
-#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr.mmio_base + 0x10)
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */
-#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
+#define EDP_PSR_STATUS _MMIO(dev_priv->psr.mmio_base + 0x40)
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
@@ -4315,10 +4315,10 @@ enum {
#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
#define EDP_PSR_STATUS_IDLE_MASK 0xf
-#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
+#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr.mmio_base + 0x44)
#define EDP_PSR_PERF_CNT_MASK 0xffffff
-#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index dc9fdb515a54..3bf887ef8573 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1135,7 +1135,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (!HAS_PSR(dev_priv))
return;
- dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+ dev_priv->psr.mmio_base = IS_HASWELL(dev_priv) ?
HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
if (!dev_priv->psr.sink_support)
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-03-21 18:01 ` [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-22 9:15 ` Jani Nikula
2019-03-21 18:01 ` [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset José Roberto de Souza
` (9 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
Right now it have a mix of PSR registers that are relative to PSR
mmio base and other register with a hardcoded address, lets keep it
consistented and have it all relative to mmio base.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28728399e607..e1ed2ba1c315 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4326,7 +4326,7 @@ enum {
#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
-#define EDP_PSR2_CTL _MMIO(0x6f900)
+#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x100)
#define EDP_PSR2_ENABLE (1 << 31)
#define EDP_SU_TRACK_ENABLE (1 << 30)
#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
@@ -4344,7 +4344,7 @@ enum {
#define EDP_PSR2_IDLE_FRAME_MASK 0xf
#define EDP_PSR2_IDLE_FRAME_SHIFT 0
-#define PSR_EVENT _MMIO(0x6F848)
+#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x48)
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
#define PSR_EVENT_PSR2_DISABLED (1 << 16)
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
@@ -4362,14 +4362,11 @@ enum {
#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
#define PSR_EVENT_PSR_DISABLE (1 << 0)
-#define EDP_PSR2_STATUS _MMIO(0x6f940)
+#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x140)
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT 28
-#define _PSR2_SU_STATUS_0 0x6F914
-#define _PSR2_SU_STATUS_1 0x6F918
-#define _PSR2_SU_STATUS_2 0x6F91C
-#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
+#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x114 + (index) * 4)
#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-03-21 18:01 ` [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct José Roberto de Souza
2019-03-21 18:01 ` [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:01 ` [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
` (8 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From BDW+ most of the PSR registers is relative to eDP transcoder
offset just PSR_IMR/IIR that have a fixed address, so lets set
mmio_base with the transcoder offset and adjust all the others
macros to the registers.
Also removing BDW_EDP_PSR_BASE from GVT because it is not used as
the only PSR register added is this one(PSR_CTL).
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++------------
drivers/gpu/drm/i915/intel_psr.c | 9 ++++++---
4 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b596cb42e24e..8163fef720bb 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2739,7 +2739,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
MMIO_D(WM_MISC, D_BDW);
- MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5f60ad4d4296..4fc5ef568ef0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -511,6 +511,7 @@ struct i915_psr {
bool enabled;
struct intel_dp *dp;
enum pipe pipe;
+ enum transcoder transcoder;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e1ed2ba1c315..3c382aee2fec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4246,9 +4246,8 @@ enum {
#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
/* HSW+ eDP PSR registers */
-#define HSW_EDP_PSR_BASE 0x64800
-#define BDW_EDP_PSR_BASE 0x6f800
-#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0)
+#define HSW_EDP_PSR_BASE 0x64000
+#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0x800)
#define EDP_PSR_ENABLE (1 << 31)
#define BDW_PSR_SINGLE_FRAME (1 << 30)
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
@@ -4281,16 +4280,16 @@ enum {
#define EDP_PSR_POST_EXIT (1 << 1)
#define EDP_PSR_PRE_ENTRY (1 << 0)
-#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr.mmio_base + 0x10)
+#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr.mmio_base + 0x810)
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x814 + (i) * 4) /* 5 registers */
-#define EDP_PSR_STATUS _MMIO(dev_priv->psr.mmio_base + 0x40)
+#define EDP_PSR_STATUS _MMIO(dev_priv->psr.mmio_base + 0x840)
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
@@ -4315,10 +4314,10 @@ enum {
#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
#define EDP_PSR_STATUS_IDLE_MASK 0xf
-#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr.mmio_base + 0x44)
+#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr.mmio_base + 0x844)
#define EDP_PSR_PERF_CNT_MASK 0xffffff
-#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */
+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x860) /* PSR_MASK on SKL+ */
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
@@ -4326,7 +4325,7 @@ enum {
#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
-#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x100)
+#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x900)
#define EDP_PSR2_ENABLE (1 << 31)
#define EDP_SU_TRACK_ENABLE (1 << 30)
#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
@@ -4344,7 +4343,7 @@ enum {
#define EDP_PSR2_IDLE_FRAME_MASK 0xf
#define EDP_PSR2_IDLE_FRAME_SHIFT 0
-#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x48)
+#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x848)
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
#define PSR_EVENT_PSR2_DISABLED (1 << 16)
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
@@ -4362,11 +4361,11 @@ enum {
#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
#define PSR_EVENT_PSR_DISABLE (1 << 0)
-#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x140)
+#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT 28
-#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x114 + (index) * 4)
+#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x914 + (index) * 4)
#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 3bf887ef8573..5fee494cd9e9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -671,6 +671,12 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
+
+ if (IS_HASWELL(dev_priv))
+ dev_priv->psr.mmio_base = HSW_EDP_PSR_BASE;
+ else
+ dev_priv->psr.mmio_base = INTEL_INFO(dev_priv)->trans_offsets[dev_priv->psr.transcoder];
DRM_DEBUG_KMS("Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
@@ -1135,9 +1141,6 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (!HAS_PSR(dev_priv))
return;
- dev_priv->psr.mmio_base = IS_HASWELL(dev_priv) ?
- HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
-
if (!dev_priv->psr.sink_support)
return;
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (2 preceding siblings ...)
2019-03-21 18:01 ` [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:01 ` [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
Even when driver is reload and hits this scenario the PSR mutex
should be initialized, otherwise reading PSR debugfs status will
execute mutex_lock() over a mutex that was not initialized.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5fee494cd9e9..acd72b6e935d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1161,7 +1161,6 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (val) {
DRM_DEBUG_KMS("PSR interruption error set\n");
dev_priv->psr.sink_not_reliable = true;
- return;
}
/* Set link_standby x link_off defaults */
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (3 preceding siblings ...)
2019-03-21 18:01 ` [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:01 ` [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
This interlaced restriction applies to all gens, not only to Haswell.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acd72b6e935d..7b8a85167c5d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -580,8 +580,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (IS_HASWELL(dev_priv) &&
- adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return;
}
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (4 preceding siblings ...)
2019-03-21 18:01 ` [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:01 ` [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
PSR support for VLV and CHV was dropped in commit ce3508fd2a77
("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
this registers around.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 36 ---------------------------------
1 file changed, 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c382aee2fec..a10475b0e336 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4209,42 +4209,6 @@ enum {
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
-/* VLV eDP PSR registers */
-#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
-#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
-#define VLV_EDP_PSR_ENABLE (1 << 0)
-#define VLV_EDP_PSR_RESET (1 << 1)
-#define VLV_EDP_PSR_MODE_MASK (7 << 2)
-#define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
-#define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
-#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
-#define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
-#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
-#define VLV_EDP_PSR_DBL_FRAME (1 << 10)
-#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
-#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
-#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
-
-#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
-#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
-#define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
-#define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
-#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
-#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
-
-#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
-#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
-#define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
-#define VLV_EDP_PSR_CURR_STATE_MASK 7
-#define VLV_EDP_PSR_DISABLED (0 << 0)
-#define VLV_EDP_PSR_INACTIVE (1 << 0)
-#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
-#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
-#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
-#define VLV_EDP_PSR_EXIT (5 << 0)
-#define VLV_EDP_PSR_IN_TRANS (1 << 7)
-#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
-
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64000
#define EDP_PSR_CTL _MMIO(dev_priv->psr.mmio_base + 0x800)
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (5 preceding siblings ...)
2019-03-21 18:01 ` [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
@ 2019-03-21 18:01 ` José Roberto de Souza
2019-03-21 18:20 ` [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders Ville Syrjälä
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: José Roberto de Souza @ 2019-03-21 18:01 UTC (permalink / raw)
To: intel-gfx
Just moving it to reduce the tabs and avoid break code lines into
several lines.
No behavior changes intended here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 63 +++++++++++++++++++--------------
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2f788291cfe0..875102eb9ed0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2701,41 +2701,50 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
return mask;
}
-static irqreturn_t
-gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+static enum irqreturn
+gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv)
{
- irqreturn_t ret = IRQ_NONE;
- u32 iir;
- enum pipe pipe;
+ u32 iir = I915_READ(GEN8_DE_MISC_IIR);
+ enum irqreturn ret = IRQ_NONE;
+ bool found = false;
- if (master_ctl & GEN8_DE_MISC_IRQ) {
- iir = I915_READ(GEN8_DE_MISC_IIR);
- if (iir) {
- bool found = false;
-
- I915_WRITE(GEN8_DE_MISC_IIR, iir);
- ret = IRQ_HANDLED;
+ if (!iir) {
+ DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+ return ret;
+ }
- if (iir & GEN8_DE_MISC_GSE) {
- intel_opregion_asle_intr(dev_priv);
- found = true;
- }
+ I915_WRITE(GEN8_DE_MISC_IIR, iir);
+ ret = IRQ_HANDLED;
- if (iir & GEN8_DE_EDP_PSR) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
+ if (iir & GEN8_DE_MISC_GSE) {
+ intel_opregion_asle_intr(dev_priv);
+ found = true;
+ }
- intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
- found = true;
- }
+ if (iir & GEN8_DE_EDP_PSR) {
+ u32 psr_iir = I915_READ(EDP_PSR_IIR);
- if (!found)
- DRM_ERROR("Unexpected DE Misc interrupt\n");
- }
- else
- DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+ intel_psr_irq_handler(dev_priv, psr_iir);
+ I915_WRITE(EDP_PSR_IIR, psr_iir);
+ found = true;
}
+ if (!found)
+ DRM_ERROR("Unexpected DE Misc interrupt\n");
+
+ return ret;
+}
+
+static irqreturn_t
+gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+{
+ irqreturn_t ret = IRQ_NONE;
+ u32 iir;
+ enum pipe pipe;
+
+ if (master_ctl & GEN8_DE_MISC_IRQ)
+ ret = gen8_de_misc_irq_handler(dev_priv);
+
if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
iir = I915_READ(GEN11_DE_HPD_IIR);
if (iir) {
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (6 preceding siblings ...)
2019-03-21 18:01 ` [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
@ 2019-03-21 18:20 ` Ville Syrjälä
2019-03-21 21:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjälä @ 2019-03-21 18:20 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Dhinakaran Pandiyan
On Thu, Mar 21, 2019 at 11:01:36AM -0700, José Roberto de Souza wrote:
> PSR is only support in eDP transcoder and there is only one instance
> of it, so lets drop all of this code.
One instance? Are you talking about PSR2?
Also the EDP transcoder is already doomed is it not?
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 17 +---
> drivers/gpu/drm/i915/intel_psr.c | 147 ++++++++-----------------------
> 2 files changed, 42 insertions(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b46910453e61..d0ca6ef6d630 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4277,13 +4277,9 @@ enum {
> /* Bspec claims those aren't shifted but stay at 0x64800 */
> #define EDP_PSR_IMR _MMIO(0x64834)
> #define EDP_PSR_IIR _MMIO(0x64838)
> -#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
> -#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
> -#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
> -#define EDP_PSR_TRANSCODER_C_SHIFT 24
> -#define EDP_PSR_TRANSCODER_B_SHIFT 16
> -#define EDP_PSR_TRANSCODER_A_SHIFT 8
> -#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
> +#define EDP_PSR_ERROR (1 << 2)
> +#define EDP_PSR_POST_EXIT (1 << 1)
> +#define EDP_PSR_PRE_ENTRY (1 << 0)
>
> #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
> #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
> @@ -4348,12 +4344,7 @@ enum {
> #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> #define EDP_PSR2_IDLE_FRAME_SHIFT 0
>
> -#define _PSR_EVENT_TRANS_A 0x60848
> -#define _PSR_EVENT_TRANS_B 0x61848
> -#define _PSR_EVENT_TRANS_C 0x62848
> -#define _PSR_EVENT_TRANS_D 0x63848
> -#define _PSR_EVENT_TRANS_EDP 0x6F848
> -#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
> +#define PSR_EVENT _MMIO(0x6F848)
> #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> #define PSR_EVENT_PSR2_DISABLED (1 << 16)
> #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 605fe8fc85cc..dc9fdb515a54 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -84,46 +84,12 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> }
> }
>
> -static int edp_psr_shift(enum transcoder cpu_transcoder)
> -{
> - switch (cpu_transcoder) {
> - case TRANSCODER_A:
> - return EDP_PSR_TRANSCODER_A_SHIFT;
> - case TRANSCODER_B:
> - return EDP_PSR_TRANSCODER_B_SHIFT;
> - case TRANSCODER_C:
> - return EDP_PSR_TRANSCODER_C_SHIFT;
> - default:
> - MISSING_CASE(cpu_transcoder);
> - /* fallthrough */
> - case TRANSCODER_EDP:
> - return EDP_PSR_TRANSCODER_EDP_SHIFT;
> - }
> -}
> -
> void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
> {
> - u32 debug_mask, mask;
> - enum transcoder cpu_transcoder;
> - u32 transcoders = BIT(TRANSCODER_EDP);
> -
> - if (INTEL_GEN(dev_priv) >= 8)
> - transcoders |= BIT(TRANSCODER_A) |
> - BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C);
> -
> - debug_mask = 0;
> - mask = 0;
> - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> - int shift = edp_psr_shift(cpu_transcoder);
> -
> - mask |= EDP_PSR_ERROR(shift);
> - debug_mask |= EDP_PSR_POST_EXIT(shift) |
> - EDP_PSR_PRE_ENTRY(shift);
> - }
> + u32 mask = EDP_PSR_ERROR;
>
> if (debug & I915_PSR_DEBUG_IRQ)
> - mask |= debug_mask;
> + mask |= EDP_PSR_POST_EXIT | EDP_PSR_PRE_ENTRY;
>
> I915_WRITE(EDP_PSR_IMR, ~mask);
> }
> @@ -167,62 +133,47 @@ static void psr_event_print(u32 val, bool psr2_enabled)
>
> void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
> {
> - u32 transcoders = BIT(TRANSCODER_EDP);
> - enum transcoder cpu_transcoder;
> - ktime_t time_ns = ktime_get();
> - u32 mask = 0;
> + ktime_t time_ns = ktime_get();
>
> - if (INTEL_GEN(dev_priv) >= 8)
> - transcoders |= BIT(TRANSCODER_A) |
> - BIT(TRANSCODER_B) |
> - BIT(TRANSCODER_C);
> -
> - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> - int shift = edp_psr_shift(cpu_transcoder);
> -
> - if (psr_iir & EDP_PSR_ERROR(shift)) {
> - DRM_WARN("[transcoder %s] PSR aux error\n",
> - transcoder_name(cpu_transcoder));
> -
> - dev_priv->psr.irq_aux_error = true;
> -
> - /*
> - * If this interruption is not masked it will keep
> - * interrupting so fast that it prevents the scheduled
> - * work to run.
> - * Also after a PSR error, we don't want to arm PSR
> - * again so we don't care about unmask the interruption
> - * or unset irq_aux_error.
> - */
> - mask |= EDP_PSR_ERROR(shift);
> - }
> + if (psr_iir & EDP_PSR_ERROR) {
> + u32 mask;
>
> - if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
> - dev_priv->psr.last_entry_attempt = time_ns;
> - DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> - transcoder_name(cpu_transcoder));
> - }
> + DRM_WARN("[transcoder %s] PSR aux error\n",
> + transcoder_name(TRANSCODER_EDP));
>
> - if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
> - dev_priv->psr.last_exit = time_ns;
> - DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> - transcoder_name(cpu_transcoder));
> + dev_priv->psr.irq_aux_error = true;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> - u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
> - bool psr2_enabled = dev_priv->psr.psr2_enabled;
> + /*
> + * If this interruption is not masked it will keep
> + * interrupting so fast that it prevents the scheduled
> + * work to run.
> + * Also after a PSR error, we don't want to arm PSR
> + * again so we don't care about unmask the interruption
> + * or unset irq_aux_error.
> + */
> + mask = I915_READ(EDP_PSR_IMR) | EDP_PSR_ERROR;
> + I915_WRITE(EDP_PSR_IMR, mask);
>
> - I915_WRITE(PSR_EVENT(cpu_transcoder), val);
> - psr_event_print(val, psr2_enabled);
> - }
> - }
> + schedule_work(&dev_priv->psr.work);
> }
>
> - if (mask) {
> - mask |= I915_READ(EDP_PSR_IMR);
> - I915_WRITE(EDP_PSR_IMR, mask);
> + if (psr_iir & EDP_PSR_PRE_ENTRY) {
> + dev_priv->psr.last_entry_attempt = time_ns;
> + DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
> + transcoder_name(TRANSCODER_EDP));
> + }
>
> - schedule_work(&dev_priv->psr.work);
> + if (psr_iir & EDP_PSR_POST_EXIT) {
> + DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
> + transcoder_name(TRANSCODER_EDP));
> +
> + if (INTEL_GEN(dev_priv) >= 9) {
> + u32 val = I915_READ(PSR_EVENT);
> + bool psr2_enabled = dev_priv->psr.psr2_enabled;
> +
> + I915_WRITE(PSR_EVENT, val);
> + psr_event_print(val, psr2_enabled);
> + }
> }
> }
>
> @@ -672,30 +623,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> dev_priv->psr.active = true;
> }
>
> -static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
> - enum transcoder cpu_transcoder)
> -{
> - static const i915_reg_t regs[] = {
> - [TRANSCODER_A] = CHICKEN_TRANS_A,
> - [TRANSCODER_B] = CHICKEN_TRANS_B,
> - [TRANSCODER_C] = CHICKEN_TRANS_C,
> - [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
> - };
> -
> - WARN_ON(INTEL_GEN(dev_priv) < 9);
> -
> - if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
> - !regs[cpu_transcoder].reg))
> - cpu_transcoder = TRANSCODER_A;
> -
> - return regs[cpu_transcoder];
> -}
> -
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 mask;
>
> /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
> @@ -706,13 +637,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
> - i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
> - cpu_transcoder);
> - u32 chicken = I915_READ(reg);
> + u32 chicken = I915_READ(CHICKEN_TRANS_EDP);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
> PSR2_ADD_VERTICAL_LINE_COUNT;
> - I915_WRITE(reg, chicken);
> + I915_WRITE(CHICKEN_TRANS_EDP, chicken);
> }
>
> /*
> @@ -1225,7 +1154,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> * to avoid any rendering problems.
> */
> val = I915_READ(EDP_PSR_IIR);
> - val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP));
> + val &= EDP_PSR_ERROR;
> if (val) {
> DRM_DEBUG_KMS("PSR interruption error set\n");
> dev_priv->psr.sink_not_reliable = true;
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (7 preceding siblings ...)
2019-03-21 18:20 ` [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders Ville Syrjälä
@ 2019-03-21 21:54 ` Patchwork
2019-03-21 21:58 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-03-21 21:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
95c7ad172d42 drm/i915/psr: Remove partial PSR support on multiple transcoders
32e9f40119c2 drm/i915: Move PSR mmio base to PSR struct
-:62: WARNING:LONG_LINE_COMMENT: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:4291:
+#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */
-:78: WARNING:LONG_LINE_COMMENT: line over 100 characters
#78: FILE: drivers/gpu/drm/i915/i915_reg.h:4321:
+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */
total: 0 errors, 2 warnings, 0 checks, 62 lines checked
f40f1d840cae drm/i915/psr: Make all PSR register relative to mmio base
32905478ea42 drm/i915/psr: Make mmio base relative to transcoder offset
-:75: WARNING:LONG_LINE_COMMENT: line over 100 characters
#75: FILE: drivers/gpu/drm/i915/i915_reg.h:4290:
+#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr.mmio_base + 0x814 + (i) * 4) /* 5 registers */
-:91: WARNING:LONG_LINE_COMMENT: line over 100 characters
#91: FILE: drivers/gpu/drm/i915/i915_reg.h:4320:
+#define EDP_PSR_DEBUG _MMIO(dev_priv->psr.mmio_base + 0x860) /* PSR_MASK on SKL+ */
-:140: WARNING:LONG_LINE: line over 100 characters
#140: FILE: drivers/gpu/drm/i915/intel_psr.c:679:
+ dev_priv->psr.mmio_base = INTEL_INFO(dev_priv)->trans_offsets[dev_priv->psr.transcoder];
total: 0 errors, 3 warnings, 0 checks, 106 lines checked
9cf701d3e3ac drm/i915/psr: Initialize PSR mutex even when sink is not reliable
79f515d2066b drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
e2bfa61adcf5 drm/i915: Remove unused VLV/CHV PSR registers
cf712ab15a65 drm/i915/bdw+: Move misc display IRQ handling to it own function
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (8 preceding siblings ...)
2019-03-21 21:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] " Patchwork
@ 2019-03-21 21:58 ` Patchwork
2019-03-21 22:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-22 16:14 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-03-21 21:58 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Remove partial PSR support on multiple transcoders
Okay!
Commit: drm/i915: Move PSR mmio base to PSR struct
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void)
Commit: drm/i915/psr: Make all PSR register relative to mmio base
Okay!
Commit: drm/i915/psr: Make mmio base relative to transcoder offset
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
Commit: drm/i915/psr: Initialize PSR mutex even when sink is not reliable
Okay!
Commit: drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
Okay!
Commit: drm/i915: Remove unused VLV/CHV PSR registers
Okay!
Commit: drm/i915/bdw+: Move misc display IRQ handling to it own function
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (9 preceding siblings ...)
2019-03-21 21:58 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-03-21 22:24 ` Patchwork
2019-03-22 16:14 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-03-21 22:24 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12556
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58373/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12556 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-bsd2:
- fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841]
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841]
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (44 -> 37)
------------------------------
Additional (2): fi-snb-2520m fi-kbl-7500u
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bxt-j4205 fi-icl-u3 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5791 -> Patchwork_12556
CI_DRM_5791: 3b6d09692ea282a3487bdf972a068d312a67ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4897: e12d69496a6bef09ac6c0f792b8d60a65cf5e0bf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12556: cf712ab15a65d677cc140e95f200aa0713dae8df @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cf712ab15a65 drm/i915/bdw+: Move misc display IRQ handling to it own function
e2bfa61adcf5 drm/i915: Remove unused VLV/CHV PSR registers
79f515d2066b drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
9cf701d3e3ac drm/i915/psr: Initialize PSR mutex even when sink is not reliable
32905478ea42 drm/i915/psr: Make mmio base relative to transcoder offset
f40f1d840cae drm/i915/psr: Make all PSR register relative to mmio base
32e9f40119c2 drm/i915: Move PSR mmio base to PSR struct
95c7ad172d42 drm/i915/psr: Remove partial PSR support on multiple transcoders
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12556/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base
2019-03-21 18:01 ` [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base José Roberto de Souza
@ 2019-03-22 9:15 ` Jani Nikula
2019-03-22 17:27 ` Dhinakaran Pandiyan
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2019-03-22 9:15 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx; +Cc: Dhinakaran Pandiyan
On Thu, 21 Mar 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> Right now it have a mix of PSR registers that are relative to PSR
> mmio base and other register with a hardcoded address, lets keep it
> consistented and have it all relative to mmio base.
This is not strictly limited to this patch, but an overall trend. The
thing that really bugs me with this is losing more of the actual
absolute mmio addresses from the file. When you're seeking to add a new
register, you can't trivially grep for it in the file anymore. Not all
of our register names match the spec (and the spec occasionally also
changes register names) so being able to find the offset is important.
When we added the macros that use ->pipe_offsets and ->trans_offsets, we
took care to have at least one of the offsets in the file. I'm wondering
if we could do something like that here as well.
BR,
Jani.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 28728399e607..e1ed2ba1c315 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4326,7 +4326,7 @@ enum {
> #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
> #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
>
> -#define EDP_PSR2_CTL _MMIO(0x6f900)
> +#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base + 0x100)
> #define EDP_PSR2_ENABLE (1 << 31)
> #define EDP_SU_TRACK_ENABLE (1 << 30)
> #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
> @@ -4344,7 +4344,7 @@ enum {
> #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> #define EDP_PSR2_IDLE_FRAME_SHIFT 0
>
> -#define PSR_EVENT _MMIO(0x6F848)
> +#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base + 0x48)
> #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> #define PSR_EVENT_PSR2_DISABLED (1 << 16)
> #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
> @@ -4362,14 +4362,11 @@ enum {
> #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
> #define PSR_EVENT_PSR_DISABLE (1 << 0)
>
> -#define EDP_PSR2_STATUS _MMIO(0x6f940)
> +#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base + 0x140)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
> #define EDP_PSR2_STATUS_STATE_SHIFT 28
>
> -#define _PSR2_SU_STATUS_0 0x6F914
> -#define _PSR2_SU_STATUS_1 0x6F918
> -#define _PSR2_SU_STATUS_2 0x6F91C
> -#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
> +#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base + 0x114 + (index) * 4)
> #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
> #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
> #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
` (10 preceding siblings ...)
2019-03-21 22:24 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-22 16:14 ` Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-03-22 16:14 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12556_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12556_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: PASS -> INCOMPLETE [fdo#109801]
* igt@gem_pwrite@big-cpu-fbr:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +114
* igt@gem_pwrite@stolen-normal:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +21
* igt@gem_stolen@stolen-pwrite:
- shard-iclb: NOTRUN -> SKIP [fdo#109277]
* igt@gem_tiled_blits@interruptible:
- shard-iclb: PASS -> TIMEOUT [fdo#109673]
* igt@i915_hangman@error-state-capture-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +2
* igt@i915_pm_rpm@i2c:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@i915_selftest@live_workarounds:
- shard-iclb: PASS -> DMESG-FAIL [fdo#108954]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +2
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9
* igt@kms_busy@extended-modeset-hang-oldfb-render-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-iclb: NOTRUN -> SKIP [fdo#109284]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: PASS -> FAIL [fdo#103355]
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +1
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: PASS -> INCOMPLETE [fdo#109507]
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +36
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#108040]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: PASS -> FAIL [fdo#103167] +8
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +28
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-iclb: PASS -> FAIL [fdo#109247] +19
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_psr@cursor_mmap_gtt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +3
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: PASS -> SKIP [fdo#109441] +5
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@perf@blocking:
- shard-iclb: PASS -> FAIL [fdo#108587]
* igt@perf@unprivileged-single-ctx-counters:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
#### Possible fixes ####
* igt@gem_tiled_pread_pwrite:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-WARN [fdo#109982] -> PASS
* igt@i915_pm_rpm@reg-read-ioctl:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@kms_atomic_transition@1x-modeset-transitions:
- shard-iclb: INCOMPLETE -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-skl: DMESG-WARN [fdo#110222] -> PASS +1
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-iclb: FAIL [fdo#103355] -> PASS
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +7
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-iclb: FAIL [fdo#109247] -> PASS +10
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@cursor_plane_move:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: DMESG-WARN [fdo#108686] -> FAIL [fdo#108686]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108587]: https://bugs.freedesktop.org/show_bug.cgi?id=108587
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5791 -> Patchwork_12556
CI_DRM_5791: 3b6d09692ea282a3487bdf972a068d312a67ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4897: e12d69496a6bef09ac6c0f792b8d60a65cf5e0bf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12556: cf712ab15a65d677cc140e95f200aa0713dae8df @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12556/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base
2019-03-22 9:15 ` Jani Nikula
@ 2019-03-22 17:27 ` Dhinakaran Pandiyan
2019-03-26 20:44 ` Souza, Jose
0 siblings, 1 reply; 16+ messages in thread
From: Dhinakaran Pandiyan @ 2019-03-22 17:27 UTC (permalink / raw)
To: Jani Nikula, José Roberto de Souza, intel-gfx
On Fri, 2019-03-22 at 11:15 +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> > Right now it have a mix of PSR registers that are relative to PSR
> > mmio base and other register with a hardcoded address, lets keep it
> > consistented and have it all relative to mmio base.
>
> This is not strictly limited to this patch, but an overall trend. The
> thing that really bugs me with this is losing more of the actual
> absolute mmio addresses from the file. When you're seeking to add a new
> register, you can't trivially grep for it in the file anymore. Not all
> of our register names match the spec (and the spec occasionally also
> changes register names) so being able to find the offset is important.
Fully agreed.
I think we can do something along the lines of
#define _HSW_PSR_OFFSET BDW_EDP_PSR_BASE - HSW_PSR_PSR_BASE
#define _BDW_PSR_CTL 0x6f800
_MMIO_HSW_ADJUST(pipe, reg) IS_HASWELL(dev_priv) ?
MMIO_TRANS2((pipe), reg - _HSW_PSR_OFFSET) : MMIO_TRANS2((pipe), reg)
#define EDP_PSR_CTL(pipe) _MMIO_HSW_ADJUST((pipe), _BDW_PSR_CTL)
I'd like at least BDW+ addresses to be in the code.
-DK
>
> When we added the macros that use ->pipe_offsets and ->trans_offsets, we
> took care to have at least one of the offsets in the file. I'm wondering
> if we could do something like that here as well.
>
> BR,
> Jani.
>
>
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 ++++-------
> > 1 file changed, 4 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 28728399e607..e1ed2ba1c315 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4326,7 +4326,7 @@ enum {
> > #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in
> > ICL+ */
> > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
> >
> > -#define EDP_PSR2_CTL _MMIO(0x6f900)
> > +#define EDP_PSR2_CTL _MMIO(dev_priv->psr.mmio_base +
> > 0x100)
> > #define EDP_PSR2_ENABLE (1 << 31)
> > #define EDP_SU_TRACK_ENABLE (1 << 30)
> > #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
> > @@ -4344,7 +4344,7 @@ enum {
> > #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> > #define EDP_PSR2_IDLE_FRAME_SHIFT 0
> >
> > -#define PSR_EVENT _MMIO(0x6F848)
> > +#define PSR_EVENT _MMIO(dev_priv->psr.mmio_base +
> > 0x48)
> > #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> > #define PSR_EVENT_PSR2_DISABLED (1 << 16)
> > #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
> > @@ -4362,14 +4362,11 @@ enum {
> > #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
> > #define PSR_EVENT_PSR_DISABLE (1 << 0)
> >
> > -#define EDP_PSR2_STATUS _MMIO(0x6f940)
> > +#define EDP_PSR2_STATUS _MMIO(dev_priv->psr.mmio_base +
> > 0x140)
> > #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
> > #define EDP_PSR2_STATUS_STATE_SHIFT 28
> >
> > -#define _PSR2_SU_STATUS_0 0x6F914
> > -#define _PSR2_SU_STATUS_1 0x6F918
> > -#define _PSR2_SU_STATUS_2 0x6F91C
> > -#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index),
> > _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
> > +#define _PSR2_SU_STATUS(index) _MMIO(dev_priv->psr.mmio_base +
> > 0x114 + (index) * 4)
> > #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
> > #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
> > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base
2019-03-22 17:27 ` Dhinakaran Pandiyan
@ 2019-03-26 20:44 ` Souza, Jose
0 siblings, 0 replies; 16+ messages in thread
From: Souza, Jose @ 2019-03-26 20:44 UTC (permalink / raw)
To: intel-gfx, Pandiyan, Dhinakaran, jani.nikula
[-- Attachment #1.1: Type: text/plain, Size: 4949 bytes --]
On Fri, 2019-03-22 at 10:27 -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2019-03-22 at 11:15 +0200, Jani Nikula wrote:
> > On Thu, 21 Mar 2019, José Roberto de Souza <jose.souza@intel.com>
> > wrote:
> > > Right now it have a mix of PSR registers that are relative to PSR
> > > mmio base and other register with a hardcoded address, lets keep
> > > it
> > > consistented and have it all relative to mmio base.
> >
> > This is not strictly limited to this patch, but an overall trend.
> > The
> > thing that really bugs me with this is losing more of the actual
> > absolute mmio addresses from the file. When you're seeking to add a
> > new
> > register, you can't trivially grep for it in the file anymore. Not
> > all
> > of our register names match the spec (and the spec occasionally
> > also
> > changes register names) so being able to find the offset is
> > important.
I understand but for new gens BSpec is using relative address see BSpec
50583 and 50577 for example.
>
> Fully agreed.
>
> I think we can do something along the lines of
>
> #define _HSW_PSR_OFFSET BDW_EDP_PSR_BASE - HSW_PSR_PSR_BASE
> #define _BDW_PSR_CTL 0x6f800
>
> _MMIO_HSW_ADJUST(pipe, reg) IS_HASWELL(dev_priv) ?
> MMIO_TRANS2((pipe), reg -
> _HSW_PSR_OFFSET) : MMIO_TRANS2((pi
> pe), reg)
To MMIO_TRANS2() work we need to give the reg based on the first
transcoder, what you think about this?
#define _HSW_EDP_PSR_BASE 0x64000
/* _PSR_CTL_A to follow BSpec naming or we could keep _PSR_CTL_A */
#define _SRD_CTL_A 0x60800
#define _SRD_CTL_EDP 0x6F800
#define EDP_PSR_CTL (_MMIO_TRANS2(dev_priv-
>psr.transcoder, _SRD_CTL_A) - dev_priv->psr.mmio_base_adjust)
intel_psr_enable_locked()
if (IS_HASWELL(dev_priv))
dev_priv->psr.mmio_base_adjust = _SRD_CTL_EDP
- _HSW_EDP_PSR_BASE;
The only concern here it that _SRD_CTL_A(and the other registers
conterparts) could give the understand that PSR could be enabled in
regular transcoders what it not the case in current gens.
>
> #define EDP_PSR_CTL(pipe) _MMIO_HSW_ADJUST((pipe), _BDW_PSR_CTL)
>
>
> I'd like at least BDW+ addresses to be in the code.
>
> -DK
>
> > When we added the macros that use ->pipe_offsets and
> > ->trans_offsets, we
> > took care to have at least one of the offsets in the file. I'm
> > wondering
> > if we could do something like that here as well.
> >
> > BR,
> > Jani.
> >
> >
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 11 ++++-------
> > > 1 file changed, 4 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 28728399e607..e1ed2ba1c315 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4326,7 +4326,7 @@ enum {
> > > #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /*
> > > Reserved in
> > > ICL+ */
> > > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+
> > > */
> > >
> > > -#define EDP_PSR2_CTL _MMIO(0x6f900)
> > > +#define EDP_PSR2_CTL _MMIO(dev_priv-
> > > >psr.mmio_base +
> > > 0x100)
> > > #define EDP_PSR2_ENABLE (1 << 31)
> > > #define EDP_SU_TRACK_ENABLE (1 << 30)
> > > #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
> > > @@ -4344,7 +4344,7 @@ enum {
> > > #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> > > #define EDP_PSR2_IDLE_FRAME_SHIFT 0
> > >
> > > -#define PSR_EVENT _MMIO(0x6F848)
> > > +#define PSR_EVENT _MMIO(dev_priv-
> > > >psr.mmio_base +
> > > 0x48)
> > > #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> > > #define PSR_EVENT_PSR2_DISABLED (1 << 16)
> > > #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
> > > @@ -4362,14 +4362,11 @@ enum {
> > > #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
> > > #define PSR_EVENT_PSR_DISABLE (1 << 0)
> > >
> > > -#define EDP_PSR2_STATUS _MMIO(0x6f940)
> > > +#define EDP_PSR2_STATUS _MMIO(dev_priv-
> > > >psr.mmio_base +
> > > 0x140)
> > > #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
> > > #define EDP_PSR2_STATUS_STATE_SHIFT 28
> > >
> > > -#define _PSR2_SU_STATUS_0 0x6F914
> > > -#define _PSR2_SU_STATUS_1 0x6F918
> > > -#define _PSR2_SU_STATUS_2 0x6F91C
> > > -#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index
> > > ),
> > > _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
> > > +#define _PSR2_SU_STATUS(index) _MMIO(dev_priv-
> > > >psr.mmio_base +
> > > 0x114 + (index) * 4)
> > > #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame
> > > ) / 3))
> > > #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
> > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff <<
> > > PSR2_SU_STATUS_SHIFT(frame))
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-03-26 20:44 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-03-21 18:01 ` [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct José Roberto de Souza
2019-03-21 18:01 ` [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base José Roberto de Souza
2019-03-22 9:15 ` Jani Nikula
2019-03-22 17:27 ` Dhinakaran Pandiyan
2019-03-26 20:44 ` Souza, Jose
2019-03-21 18:01 ` [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset José Roberto de Souza
2019-03-21 18:01 ` [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
2019-03-21 18:01 ` [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
2019-03-21 18:01 ` [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
2019-03-21 18:01 ` [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-03-21 18:20 ` [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders Ville Syrjälä
2019-03-21 21:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] " Patchwork
2019-03-21 21:58 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-21 22:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-22 16:14 ` ✓ Fi.CI.IGT: " Patchwork
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