[PATCH 1/2] drm/i915: Turn dram_info.num_channels into a bitmask

[PATCH 1/2] drm/i915: Turn dram_info.num_channels into a bitmask

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to know out which channels are actually occupied so that
later on we can read the memory timings from the right registers.
To that end convert num_channels into a bitmask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 28 +++++++++++++++-------------
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e380cd317dc..8b37ec0e0676 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1209,14 +1209,14 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 	if (ret == 0)
-		dram_info->num_channels++;
+		dram_info->channels |= BIT(0);
 
 	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 	if (ret == 0)
-		dram_info->num_channels++;
+		dram_info->channels |= BIT(1);
 
-	if (dram_info->num_channels == 0) {
+	if (dram_info->channels == 0) {
 		DRM_INFO("Number of memory channels is zero\n");
 		return -EINVAL;
 	}
@@ -1285,8 +1285,8 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
 	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
-	dram_info->bandwidth_kbps = dram_info->num_channels *
-							mem_freq_khz * 8;
+	dram_info->bandwidth_kbps = mem_freq_khz *
+		hweight8(dram_info->channels) * 8;
 
 	if (dram_info->bandwidth_kbps == 0) {
 		DRM_INFO("Couldn't get system memory bandwidth\n");
@@ -1380,20 +1380,20 @@ static int
 bxt_get_dram_info(struct drm_i915_private *dev_priv)
 {
 	struct dram_info *dram_info = &dev_priv->dram_info;
-	u32 dram_channels;
 	u32 mem_freq_khz, val;
-	u8 num_active_channels;
+	u8 num_channels = 0;
 	int i;
 
 	val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
 	mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
 				    BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
-	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
-	num_active_channels = hweight32(dram_channels);
+	dram_info->channels = (val & BXT_DRAM_CHANNEL_ACTIVE_MASK) >>
+		BXT_DRAM_CHANNEL_ACTIVE_SHIFT;
 
 	/* Each active bit represents 4-byte channel */
-	dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
+	dram_info->bandwidth_kbps = mem_freq_khz *
+		hweight8(dram_info->channels) * 4;
 
 	if (dram_info->bandwidth_kbps == 0) {
 		DRM_INFO("Couldn't get system memory bandwidth\n");
@@ -1411,7 +1411,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 		if (val == 0xFFFFFFFF)
 			continue;
 
-		dram_info->num_channels++;
+		num_channels++;
 
 		bxt_get_dimm_info(&dimm, val);
 		type = bxt_get_dimm_type(val);
@@ -1439,6 +1439,8 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 			dram_info->type = type;
 	}
 
+	WARN_ON(num_channels != hweight8(dram_info->channels));
+
 	if (dram_info->type == INTEL_DRAM_UNKNOWN ||
 	    dram_info->ranks == 0) {
 		DRM_INFO("couldn't get memory information\n");
@@ -1472,9 +1474,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 	if (ret)
 		return;
 
-	DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
+	DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: 0x%x\n",
 		      dram_info->bandwidth_kbps,
-		      dram_info->num_channels);
+		      dram_info->channels);
 
 	DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
 		      dram_info->ranks, yesno(dram_info->is_16gb_dimm));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 363b2d3e4d50..f638c0c74955 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1832,7 +1832,7 @@ struct drm_i915_private {
 	struct dram_info {
 		bool valid;
 		bool is_16gb_dimm;
-		u8 num_channels;
+		u8 channels; /* bitmask */
 		u8 ranks;
 		u32 bandwidth_kbps;
 		bool symmetric_memory;
-- 
2.19.2

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[PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ICL has so many planes that it can easily exceed the maximum
effective memory bandwidth of the system. We must therefore check
that we don't exceed that limit.

The algorithm is very magic number heavy and lacks sufficient
explanation for now. We also have no sane way to query the
memory clock and timings, so we must rely on a combination of
raw readout from the memory controller and hardcoded assumptions.
The memory controller values obviously change as the system
jumps between the different SAGV points, so we try to stabilize
it first by disabling SAGV for the duration of the readout.

The utilized bandwidth is tracked via a device wide atomic
private object. That is actually not robust because we can't
afford to enforce strict global ordering between the pipes.
Thus I think I'll need to change this to simply chop up the
available bandwidth between all the active pipes. Each pipe
can then do whatever it wants as long as it doesn't exceed
its budget. That scheme will also require that we assume that
any number of planes could be active at any time.

TODO: make it robust and deal with all the open questions

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/Makefile             |   1 +
 drivers/gpu/drm/i915/i915_drv.c           | 346 ++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h           |  10 +
 drivers/gpu/drm/i915/intel_atomic_plane.c |  20 ++
 drivers/gpu/drm/i915/intel_bw.c           | 190 ++++++++++++
 drivers/gpu/drm/i915/intel_display.c      |  39 ++-
 drivers/gpu/drm/i915/intel_drv.h          |  32 ++
 7 files changed, 637 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_bw.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 68fecf355471..2d24bdd501c4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,7 @@ i915-y += intel_audio.o \
 	  intel_atomic.o \
 	  intel_atomic_plane.o \
 	  intel_bios.o \
+	  intel_bw.o \
 	  intel_cdclk.o \
 	  intel_color.o \
 	  intel_combo_phy.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8b37ec0e0676..134d1b1a93f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1451,6 +1451,348 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
+#define  SKL_QCLK_RATIO_MASK (0x7f << 0)
+#define  SKL_QCLK_RATIO_SHIT 0
+#define  SKL_QCLK_REFERENCE (1 << 7)
+#define  CNL_QCLK_RATIO_MASK (0x7f << 2)
+#define  CNL_QCLK_RATIO_SHIT 2
+#define  CNL_QCLK_REFERENCE (1 << 9)
+#define  ICL_QCLK_RATIO_MASK (0xff << 2)
+#define  ICL_QCLK_RATIO_SHIT 2
+#define  ICL_QCLK_REFERENCE (1 << 10)
+
+#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
+#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
+#define  SKL_DRAM_T_WRPRE_MASK (0x7f << 24)
+#define  SKL_DRAM_T_WRPRE_SHIFT 24
+#define  SKL_DRAM_T_RDPRE_MASK (0xf << 16)
+#define  SKL_DRAM_T_RDPRE_SHIFT 16
+#define  SKL_DRAM_T_RAS_MASK (0x7f << 8)
+#define  SKL_DRAM_T_RAS_SHIFT 8
+#define  SKL_DRAM_T_RPAB_EXT_MASK (0x3 << 6)
+#define  SKL_DRAM_T_RPAB_EXT_SHIFT 6
+#define  SKL_DRAM_T_RP_MASK (0x3f << 0)
+#define  SKL_DRAM_T_RP_SHIFT 0
+#define  CNL_DRAM_T_WRPRE_MASK (0xff << 24)
+#define  CNL_DRAM_T_WRPRE_SHIFT 24
+#define  CNL_DRAM_T_PPD_MASK (0x7 << 21)
+#define  CNL_DRAM_T_PPD_SHIFT 21
+#define  CNL_DRAM_T_RDPRE_MASK (0x1f << 16)
+#define  CNL_DRAM_T_RDPRE_SHIFT 16
+#define  CNL_DRAM_T_RAS_MASK (0x7f << 9)
+#define  CNL_DRAM_T_RAS_SHIFT 9
+#define  CNL_DRAM_T_RPAB_EXT_MASK (0x7 << 6)
+#define  CNL_DRAM_T_RPAB_EXT_SHIFT 6
+#define  CNL_DRAM_T_RP_MASK (0x3f << 0)
+#define  CNL_DRAM_T_RP_SHIFT 0
+
+struct intel_dram_timings {
+	u8 t_rp, t_rdpre, t_ras, t_bl;
+};
+
+static int icl_get_dclk(struct drm_i915_private *dev_priv)
+{
+	int ratio, ref;
+	u32 val;
+
+	val = I915_READ(SA_PERF_STATUS_0_0_0_MCHBAR_PC);
+
+	DRM_DEBUG_KMS("SA_PERF = 0x%x\n", val);
+	DRM_DEBUG_KMS("BIOS_DATA = 0x%x\n",
+		      I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU));
+
+	ratio = (val & ICL_QCLK_RATIO_MASK) >> ICL_QCLK_RATIO_SHIT;
+
+	if (val & ICL_QCLK_REFERENCE)
+		ref = 6; /* 6 * 16.666 MHz = 100 MHz */
+	else
+		ref = 8; /* 8 * 16.666 MHz = 133 MHz */
+
+	return ratio * ref;
+}
+
+#if 0
+static void skl_get_dram_ch_timings(struct intel_dram_timings *t,
+				    int channel, enum intel_dram_type type,
+				    u32 val)
+{
+	t->t_rp = (val & SKL_DRAM_T_RP_MASK) >> SKL_DRAM_T_RP_SHIFT;
+	t->t_rdpre = (val & SKL_DRAM_T_RDPRE_MASK) >> SKL_DRAM_T_RDPRE_SHIFT;
+	t->t_ras = (val & SKL_DRAM_T_RAS_MASK) >> SKL_DRAM_T_RAS_SHIFT;
+	t->t_bl = type == INTEL_DRAM_DDR4 ? 4 : 8;
+
+	DRM_DEBUG_KMS("CH%d tRP=%d tRDPRE=%d tRAS=%d tBL=%d\n",
+		      channel, t->t_rp, t->t_rdpre, t->t_ras, t->t_bl);
+}
+
+static void skl_get_dram_timings(struct drm_i915_private *dev_priv,
+				 const struct dram_info *dram,
+				 struct intel_dram_timings *t)
+{
+	if (dram->channels & BIT(0)) {
+		u32 val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+
+		skl_get_dram_ch_timings(t, 0, dram->type, val);
+	} else if (dram->channels & BIT(1)) {
+		u32 val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
+
+		skl_get_dram_ch_timings(t, 1, dram->type, val);
+	}
+}
+#endif
+
+static void cnl_get_dram_ch_timings(struct intel_dram_timings *t,
+				    int channel, enum intel_dram_type type,
+				    u32 val)
+{
+	t->t_rp = (val & CNL_DRAM_T_RP_MASK) >> CNL_DRAM_T_RP_SHIFT;
+	t->t_rdpre = (val & CNL_DRAM_T_RDPRE_MASK) >> CNL_DRAM_T_RDPRE_SHIFT;
+	t->t_ras = (val & CNL_DRAM_T_RAS_MASK) >> CNL_DRAM_T_RAS_SHIFT;
+	t->t_bl = type == INTEL_DRAM_DDR4 ? 4 : 8;
+
+	DRM_DEBUG_KMS("CH%d tRP=%d tRDPRE=%d tRAS=%d tBL=%d\n",
+		      channel, t->t_rp, t->t_rdpre, t->t_ras, t->t_bl);
+}
+
+static void cnl_get_dram_timings(struct drm_i915_private *dev_priv,
+				 const struct dram_info *dram,
+				 struct intel_dram_timings *t)
+{
+	u32 val;
+
+	if (dram->channels & BIT(0)) {
+		val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+		cnl_get_dram_ch_timings(t, 0, dram->type, val);
+	} else if (dram->channels & BIT(1)) {
+		val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
+		cnl_get_dram_ch_timings(t, 1, dram->type, val);
+	}
+}
+
+struct intel_sagv_point {
+	u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
+};
+
+struct intel_sagv_info {
+	struct intel_sagv_point points[3];
+	int num_points;
+};
+
+static void icl_get_sagv_points(struct drm_i915_private *dev_priv,
+				struct intel_sagv_info *si,
+				const struct intel_dram_timings *t)
+{
+	int dclk, i;
+
+	dclk = icl_get_dclk(dev_priv);
+
+	si->num_points = 3;
+
+	/*
+	 * ICL Hardcoded
+	 * Name  Description         MC clock(MHz)     DDR data rate(MT / s)  Gear
+	 * Low   Min voltage point   1066              2133                   2
+	 * Med   Max DDR rate point  Max DDR freq / 2  Max DDR freq           2
+	 * High  Min latency point   2667              Same as MC clock       1
+	 */
+	si->points[0].dclk = min(64, dclk);
+	si->points[1].dclk = dclk;
+	si->points[2].dclk = min(80, dclk);
+
+	for (i = 0; i < si->num_points; i++) {
+		struct intel_sagv_point *sp = &si->points[i];
+
+		/*
+		 * We assume these scale linearly.
+		 * Seems to match observed behaviour.
+		 */
+		sp->t_rp = DIV_ROUND_UP(t->t_rp * sp->dclk, dclk);
+		sp->t_rdpre = DIV_ROUND_UP(t->t_rdpre * sp->dclk, dclk);
+		sp->t_ras = DIV_ROUND_UP(t->t_ras * sp->dclk, dclk);
+
+		sp->t_rcd = sp->t_rp;
+		sp->t_rc = sp->t_rp + sp->t_ras;
+
+		DRM_DEBUG_KMS("SAGV %d DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
+			      i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
+			      sp->t_rcd, sp->t_rc);
+	}
+}
+
+static int icl_calc_bw(int dclk, int num, int den)
+{
+	/* multiples of 2 x 16.666MHz (100/6) */
+	return DIV_ROUND_CLOSEST(num * dclk * 2 * 100, den * 6);
+}
+
+static int icl_sagv_max_dclk(const struct intel_sagv_info *si)
+{
+	u16 dclk = 0;
+	int i;
+
+	for (i = 0; i < si->num_points; i++)
+		dclk = max(dclk, si->points[i].dclk);
+
+	return dclk;
+}
+
+struct intel_sa_info {
+	u8 deburst, mpagesize, deprogbwlimit, displayrtids;
+};
+
+static const struct intel_sa_info icl_sa_info = {
+	.deburst = 8,
+	.mpagesize = 16,
+	.deprogbwlimit = 25, /* GB/s */
+	.displayrtids = 128,
+};
+
+static void icl_get_bw_info(struct drm_i915_private *dev_priv)
+{
+	const struct dram_info *dram = &dev_priv->dram_info;
+	struct intel_sagv_info si = {};
+	struct intel_dram_timings t = {};
+	const struct intel_sa_info *sa = &icl_sa_info;
+	bool is_y_tile = true; /* assume y tile may be used */
+	int num_channels = hweight8(dram->channels);
+	int deinterleave;
+#if 0
+	int clpchpblock;
+	int pagelimit;
+#endif
+	int ipqdepth, ipqdepthpch;
+	int dclk_max;
+	int maxdebw;
+	int i;
+
+	/*
+	 * Try to muzzle SAGV to prevent it from
+	 * messing up the memory controller readout.
+	 */
+	intel_disable_sagv(dev_priv);
+
+	/*
+	 * Magic sleep to avoid observing very high DDR clock.
+	 * Not sure what's going on but on a system with DDR4-3200
+	 * clock of 4800 MT/s is often observed here. A short
+	 * sleep manages to hide that.. Is that actually
+	 * the "min latency" SAGV point?. Maybe the SA clocks
+	 * things way up when there is no memory traffic?
+	 * But polling the register never seems to show this
+	 * except during i915 unload/load. Sleeping before the
+	 * SAGV disable usually returns 2133 MT/s.
+	 *
+	 * FIXME what is going on?
+	 */
+	msleep(5);
+
+	cnl_get_dram_timings(dev_priv, dram, &t);
+
+	icl_get_sagv_points(dev_priv, &si, &t);
+
+	deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
+	dclk_max = icl_sagv_max_dclk(&si);
+
+	ipqdepthpch = 16;
+
+	maxdebw = min(sa->deprogbwlimit * 1000,
+		      icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */
+#if 0
+	clpchpblock = deinterleave * 8 / num_channels;
+	pagelimit = sa->mpagesize * deinterleave * 2 / num_channels;
+#endif
+	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+
+	DRM_DEBUG_KMS("maxdebw = %d\n", maxdebw);
+	DRM_DEBUG_KMS("ipqdepth = %d\n", ipqdepth);
+	DRM_DEBUG_KMS("deinterleave = %d\n", deinterleave);
+	DRM_DEBUG_KMS("dclk_max = %d\n", dclk_max);
+
+	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+		struct intel_bw_info *bi = &dev_priv->max_bw[i];
+		int clpchgroup;
+		int j;
+
+		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
+		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
+
+		DRM_DEBUG_KMS("clpchgroup = %d\n", clpchgroup);
+		DRM_DEBUG_KMS("num_planes = %d\n", bi->num_planes);
+
+		for (j = 0; j < si.num_points; j++) {
+			const struct intel_sagv_point *sp = &si.points[j];
+			int ct, bw;
+
+			/*
+			 * Max row cycle time
+			 *
+			 * FIXME what is the logic behind the
+			 * assumed burst length?
+			 */
+			ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
+				   (clpchgroup - 1) * t.t_bl + sp->t_rdpre);
+			bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
+
+			DRM_DEBUG_KMS("ct = %d\n", ct);
+			DRM_DEBUG_KMS("bw = %d\n", bw);
+
+			bi->deratedbw[j] = min(maxdebw,
+					       bw * 9 / 10); /* 90% */
+		}
+
+		if (bi->num_planes == 1)
+			break;
+	}
+}
+
+static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
+			       int num_planes, int sagv)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+		const struct intel_bw_info *bi =
+			&dev_priv->max_bw[i];
+
+		if (num_planes >= bi->num_planes)
+			return bi->deratedbw[sagv];
+	}
+
+	return 0;
+}
+
+unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
+				 int num_planes)
+{
+	if (IS_ICELAKE(dev_priv))
+		/*
+		 * FIXME with SAGV disabled maybe we can assume
+		 * point 1 will always be used? Seems to match
+		 * the behaviour observed in the wild.
+		 */
+		return min3(icl_max_bw(dev_priv, num_planes, 0),
+			    icl_max_bw(dev_priv, num_planes, 1),
+			    icl_max_bw(dev_priv, num_planes, 2));
+	else
+		return UINT_MAX;
+}
+
+static void icl_dump_max_bw(struct drm_i915_private *dev_priv)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+		const struct intel_bw_info *bi = &dev_priv->max_bw[i];
+		int j;
+
+		for (j = 0; j < ARRAY_SIZE(bi->deratedbw); j++) {
+			DRM_DEBUG_KMS("BW%d SAGV%d: num_planes=%d deratedbw=%d\n",
+				      i, j, bi->num_planes, bi->deratedbw[j]);
+		}
+	}
+}
+
 static void
 intel_get_dram_info(struct drm_i915_private *dev_priv)
 {
@@ -1629,6 +1971,10 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	 */
 	intel_get_dram_info(dev_priv);
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		icl_get_bw_info(dev_priv);
+		icl_dump_max_bw(dev_priv);
+	}
 
 	return 0;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f638c0c74955..825bea3176fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -54,6 +54,7 @@
 #include <drm/drm_cache.h>
 #include <drm/drm_util.h>
 #include <drm/drm_dsc.h>
+#include <drm/drm_atomic.h>
 #include <drm/drm_connector.h>
 #include <drm/i915_mei_hdcp_interface.h>
 
@@ -1845,6 +1846,13 @@ struct drm_i915_private {
 		} type;
 	} dram_info;
 
+	struct intel_bw_info {
+		int num_planes;
+		int deratedbw[3];
+	} max_bw[6];
+
+	struct drm_private_obj bw_obj;
+
 	struct i915_runtime_pm runtime_pm;
 
 	struct {
@@ -2634,6 +2642,8 @@ extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
+unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
+				 int num_planes);
 
 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
 int intel_engines_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 9d32a6fcf840..de6b23ee6306 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -111,6 +111,22 @@ intel_plane_destroy_state(struct drm_plane *plane,
 	drm_atomic_helper_plane_destroy_state(plane, state);
 }
 
+unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
+				   const struct intel_plane_state *plane_state)
+{
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	unsigned int cpp = 0;
+	int i;
+
+	if (!plane_state->base.visible)
+		return 0;
+
+	for (i = 0; i < fb->format->num_planes; i++)
+		cpp += fb->format->cpp[i];
+
+	return cpp * crtc_state->pixel_rate;
+}
+
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 					struct intel_crtc_state *new_crtc_state,
 					const struct intel_plane_state *old_plane_state,
@@ -122,6 +138,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	new_crtc_state->active_planes &= ~BIT(plane->id);
 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
 	new_crtc_state->c8_planes &= ~BIT(plane->id);
+	new_crtc_state->data_rate[plane->id] = 0;
 	new_plane_state->base.visible = false;
 
 	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
@@ -146,6 +163,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	if (new_plane_state->base.visible || old_plane_state->base.visible)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
+	new_crtc_state->data_rate[plane->id] =
+		intel_plane_data_rate(new_crtc_state, new_plane_state);
+
 	return intel_plane_atomic_calc_changes(old_crtc_state,
 					       &new_crtc_state->base,
 					       old_plane_state,
diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
new file mode 100644
index 000000000000..bd722fe5fccb
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_bw.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include <drm/drm_atomic_state_helper.h>
+
+#include "intel_drv.h"
+
+static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * We assume cursors are small enough
+	 * to not not cause bandwidth problems.
+	 */
+	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
+}
+
+static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	unsigned int data_rate = 0;
+	enum plane_id plane_id;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		/*
+		 * We assume cursors are small enough
+		 * to not not cause bandwidth problems.
+		 */
+		if (plane_id == PLANE_CURSOR)
+			continue;
+
+		data_rate += crtc_state->data_rate[plane_id];
+	}
+
+	return data_rate;
+}
+
+void intel_bw_crtc_update(struct intel_bw_state *bw_state,
+			  const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	bw_state->data_rate[crtc->pipe] =
+		intel_bw_crtc_data_rate(crtc_state);
+	bw_state->num_active_planes[crtc->pipe] =
+		intel_bw_crtc_num_active_planes(crtc_state);
+
+	DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
+		      pipe_name(crtc->pipe),
+		      bw_state->data_rate[crtc->pipe],
+		      bw_state->num_active_planes[crtc->pipe]);
+}
+
+static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
+					       const struct intel_bw_state *bw_state)
+{
+	unsigned int num_active_planes = 0;
+	enum pipe pipe;
+
+	for_each_pipe(dev_priv, pipe) {
+		num_active_planes += bw_state->num_active_planes[pipe];
+
+		DRM_DEBUG_KMS("pipe %c num active planes %u\n",
+			      pipe_name(pipe),
+			      bw_state->num_active_planes[pipe]);
+	}
+
+	return num_active_planes;
+}
+
+static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+				       const struct intel_bw_state *bw_state)
+{
+	unsigned int data_rate = 0;
+	enum pipe pipe;
+
+	for_each_pipe(dev_priv, pipe) {
+		data_rate += bw_state->data_rate[pipe];
+
+		DRM_DEBUG_KMS("pipe %c data rate %u\n",
+			      pipe_name(pipe),
+			      bw_state->data_rate[pipe]);
+	}
+
+	return data_rate;
+}
+
+int intel_bw_atomic_check(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+	struct intel_bw_state *bw_state = NULL;
+	unsigned int data_rate, max_data_rate;
+	unsigned int num_active_planes;
+	struct intel_crtc *crtc;
+	int i;
+
+	/* FIXME earlier gens need some checks too */
+	if (INTEL_GEN(dev_priv) < 11)
+		return 0;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		unsigned int old_data_rate =
+			intel_bw_crtc_data_rate(old_crtc_state);
+		unsigned int new_data_rate =
+			intel_bw_crtc_data_rate(new_crtc_state);
+		unsigned int old_active_planes =
+			intel_bw_crtc_num_active_planes(old_crtc_state);
+		unsigned int new_active_planes =
+			intel_bw_crtc_num_active_planes(new_crtc_state);
+
+		/*
+		 * Avoid locking the bw state when
+		 * nothing significant has changed.
+		 */
+		if (old_data_rate == new_data_rate &&
+		    old_active_planes == new_active_planes)
+			continue;
+
+		bw_state  = intel_atomic_get_bw_state(state);
+		if (IS_ERR(bw_state))
+			return PTR_ERR(bw_state);
+
+		bw_state->data_rate[crtc->pipe] = new_data_rate;
+		bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+
+		DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
+			      pipe_name(crtc->pipe),
+			      bw_state->data_rate[crtc->pipe],
+			      bw_state->num_active_planes[crtc->pipe]);
+	}
+
+	if (!bw_state)
+		return 0;
+
+	data_rate = intel_bw_data_rate(dev_priv, bw_state);
+	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+
+	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+
+	data_rate = DIV_ROUND_UP(data_rate, 1000);
+
+	if (data_rate > max_data_rate) {
+		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
+			      data_rate, max_data_rate, num_active_planes);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj)
+{
+	struct intel_bw_state *state;
+
+	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return NULL;
+
+	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
+
+	return &state->base;
+}
+
+static void intel_bw_destroy_state(struct drm_private_obj *obj,
+				   struct drm_private_state *state)
+{
+	kfree(state);
+}
+
+static const struct drm_private_state_funcs intel_bw_funcs = {
+	.atomic_duplicate_state = intel_bw_duplicate_state,
+	.atomic_destroy_state = intel_bw_destroy_state,
+};
+
+int intel_bw_init(struct drm_i915_private *dev_priv)
+{
+	struct intel_bw_state *state;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj,
+				    &state->base, &intel_bw_funcs);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01cdd6e745c3..272ea87bc070 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2828,6 +2828,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 
 	intel_set_plane_visible(crtc_state, plane_state, false);
 	fixup_active_planes(crtc_state);
+	crtc_state->data_rate[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY)
 		intel_pre_disable_primary_noatomic(&crtc->base);
@@ -6502,6 +6503,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 	struct intel_encoder *encoder;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_bw_state *bw_state =
+		to_intel_bw_state(dev_priv->bw_obj.state);
 	enum intel_display_power_domain domain;
 	struct intel_plane *plane;
 	u64 domains;
@@ -6564,6 +6567,9 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 	dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
 	dev_priv->min_cdclk[intel_crtc->pipe] = 0;
 	dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
+
+	bw_state->data_rate[intel_crtc->pipe] = 0;
+	bw_state->num_active_planes[intel_crtc->pipe] = 0;
 }
 
 /*
@@ -11066,6 +11072,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 	if (!is_crtc_enabled) {
 		plane_state->visible = visible = false;
 		to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
+		to_intel_crtc_state(crtc_state)->data_rate[plane->id] = 0;
 	}
 
 	if (!was_visible && !visible)
@@ -13156,7 +13163,15 @@ static int intel_atomic_check(struct drm_device *dev,
 		return ret;
 
 	intel_fbc_choose_crtc(dev_priv, intel_state);
-	return calc_watermark_data(intel_state);
+	ret = calc_watermark_data(intel_state);
+	if (ret)
+		return ret;
+
+	ret = intel_bw_atomic_check(intel_state);
+	if (ret)
+		return ret;
+
+	return 0;
 }
 
 static int intel_atomic_prepare_commit(struct drm_device *dev,
@@ -15533,6 +15548,10 @@ int intel_modeset_init(struct drm_device *dev)
 
 	drm_mode_config_init(dev);
 
+	ret = intel_bw_init(dev_priv);
+	if (ret)
+		return ret;
+
 	dev->mode_config.min_width = 0;
 	dev->mode_config.min_height = 0;
 
@@ -16155,8 +16174,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	drm_connector_list_iter_end(&conn_iter);
 
 	for_each_intel_crtc(dev, crtc) {
+		struct intel_bw_state *bw_state =
+			to_intel_bw_state(dev_priv->bw_obj.state);
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
+		struct intel_plane *plane;
 		int min_cdclk = 0;
 
 		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
@@ -16195,6 +16217,21 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		dev_priv->min_voltage_level[crtc->pipe] =
 			crtc_state->min_voltage_level;
 
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			const struct intel_plane_state *plane_state =
+				to_intel_plane_state(plane->base.state);
+
+			/*
+			 * FIXME don't have the fb yet, so can't
+			 * use intel_plane_data_rate() :(
+			 */
+			if (plane_state->base.visible)
+				crtc_state->data_rate[plane->id] =
+					4 * crtc_state->pixel_rate;
+		}
+
+		intel_bw_crtc_update(bw_state, crtc_state);
+
 		intel_pipe_config_sanity_check(dev_priv, crtc_state);
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4d7ae579fc92..6f3422f4690f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1018,6 +1018,8 @@ struct intel_crtc_state {
 
 	struct intel_crtc_wm_state wm;
 
+	u32 data_rate[I915_MAX_PLANES];
+
 	/* Gamma mode programmed on the pipe */
 	u32 gamma_mode;
 
@@ -1181,6 +1183,7 @@ struct cxsr_latency {
 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
+#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
 
 struct intel_hdmi {
 	i915_reg_t hdmi_reg;
@@ -2485,11 +2488,34 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 	return to_intel_crtc_state(crtc_state);
 }
 
+struct intel_bw_state {
+	struct drm_private_state base;
+
+	unsigned int data_rate[I915_MAX_PIPES];
+	u8 num_active_planes[I915_MAX_PIPES];
+};
+
+static inline struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct drm_private_state *bw_state;
+
+	bw_state = drm_atomic_get_private_obj_state(&state->base,
+						    &dev_priv->bw_obj);
+	if (IS_ERR(bw_state))
+		return ERR_CAST(bw_state);
+
+	return to_intel_bw_state(bw_state);
+}
+
 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 			       struct intel_crtc *intel_crtc,
 			       struct intel_crtc_state *crtc_state);
 
 /* intel_atomic_plane.c */
+unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
+				   const struct intel_plane_state *plane_state);
 void intel_update_plane(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
@@ -2513,6 +2539,12 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 					const struct intel_plane_state *old_plane_state,
 					struct intel_plane_state *intel_state);
 
+/* intel_bw.c */
+int intel_bw_init(struct drm_i915_private *dev_priv);
+int intel_bw_atomic_check(struct intel_atomic_state *state);
+void intel_bw_crtc_update(struct intel_bw_state *bw_state,
+			  const struct intel_crtc_state *crtc_state);
+
 /* intel_color.c */
 void intel_color_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
-- 
2.19.2

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Re: [PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

[Lisovskiy, Stanislav]

On Wed, 2019-03-20 at 23:46 +0200, Ville Syrjala wrote:
> +static void cnl_get_dram_timings(struct drm_i915_private *dev_priv,
> +                                const struct dram_info *dram,
> +                                struct intel_dram_timings *t)
> +{
> +       u32 val;
> +
> +       if (dram->channels & BIT(0)) {
> +               val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> +               cnl_get_dram_ch_timings(t, 0, dram->type, val);
> +       } else if (dram->channels & BIT(1)) {
> +               val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
> +               cnl_get_dram_ch_timings(t, 1, dram->type, val);
> +       }
> +}

So if have now dram->channels as a bit mask, can't it be so
that we have both enabled and what will happen then?

This code will always use channel 0 timings in that case as I
understand, is it expected to work this way?

Also, if it is always either one or another, then we probably don't
need "else if" here.

Best Regards,

Lisovskiy Stanislav
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Re: [PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

[Ville Syrjälä]

On Thu, Mar 21, 2019 at 09:34:00AM +0000, Lisovskiy, Stanislav wrote:
> On Wed, 2019-03-20 at 23:46 +0200, Ville Syrjala wrote:
> > +static void cnl_get_dram_timings(struct drm_i915_private *dev_priv,
> > +                                const struct dram_info *dram,
> > +                                struct intel_dram_timings *t)
> > +{
> > +       u32 val;
> > +
> > +       if (dram->channels & BIT(0)) {
> > +               val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> > +               cnl_get_dram_ch_timings(t, 0, dram->type, val);
> > +       } else if (dram->channels & BIT(1)) {
> > +               val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
> > +               cnl_get_dram_ch_timings(t, 1, dram->type, val);
> > +       }
> > +}
> 
> So if have now dram->channels as a bit mask, can't it be so
> that we have both enabled and what will happen then?
> 
> This code will always use channel 0 timings in that case as I
> understand, is it expected to work this way?

It seemed to be fine when I tested it (ie. it always picked the slower
timings when I had mixed DIMMs in the system). But I think I have to
retest that one more time to make sure SAGV wasn't playing tricks on me.

> 
> Also, if it is always either one or another, then we probably don't
> need "else if" here.
> 
> Best Regards,
> 
> Lisovskiy Stanislav

-- 
Ville Syrjälä
Intel
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Re: [PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

[Ville Syrjälä]

On Wed, Mar 20, 2019 at 11:46:35PM +0200, Ville Syrjala wrote:
> +	/*
> +	 * Try to muzzle SAGV to prevent it from
> +	 * messing up the memory controller readout.
> +	 */
> +	intel_disable_sagv(dev_priv);
> +
> +	/*
> +	 * Magic sleep to avoid observing very high DDR clock.
> +	 * Not sure what's going on but on a system with DDR4-3200
> +	 * clock of 4800 MT/s is often observed here. A short
> +	 * sleep manages to hide that.. Is that actually
> +	 * the "min latency" SAGV point?. Maybe the SA clocks
> +	 * things way up when there is no memory traffic?
> +	 * But polling the register never seems to show this
> +	 * except during i915 unload/load. Sleeping before the
> +	 * SAGV disable usually returns 2133 MT/s.
> +	 *
> +	 * FIXME what is going on?
> +	 */
> +	msleep(5);

Argh. Looks like this isn't working on the ci machines. We get

<7>[   12.419386] [drm:i915_driver_load [i915]] SAGV 0 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50
<7>[   12.419417] [drm:i915_driver_load [i915]] SAGV 1 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50
<7>[   12.419447] [drm:i915_driver_load [i915]] SAGV 2 DCLK=64 tRP=15 tRDPRE=8 tRAS=35 tRCD=15 tRC=50

Which would indicate 2133 MT/s even though the machines have
3200 MT/s memory (at least according to DMI).

-- 
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Intel
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Re: [PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL

[Maarten Lankhorst]

Op 20-03-2019 om 22:46 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL has so many planes that it can easily exceed the maximum
> effective memory bandwidth of the system. We must therefore check
> that we don't exceed that limit.
>
> The algorithm is very magic number heavy and lacks sufficient
> explanation for now. We also have no sane way to query the
> memory clock and timings, so we must rely on a combination of
> raw readout from the memory controller and hardcoded assumptions.
> The memory controller values obviously change as the system
> jumps between the different SAGV points, so we try to stabilize
> it first by disabling SAGV for the duration of the readout.
>
> The utilized bandwidth is tracked via a device wide atomic
> private object. That is actually not robust because we can't
> afford to enforce strict global ordering between the pipes.
> Thus I think I'll need to change this to simply chop up the
> available bandwidth between all the active pipes. Each pipe
> can then do whatever it wants as long as it doesn't exceed
> its budget. That scheme will also require that we assume that
> any number of planes could be active at any time.
>
> TODO: make it robust and deal with all the open questions
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile             |   1 +
>  drivers/gpu/drm/i915/i915_drv.c           | 346 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h           |  10 +
>  drivers/gpu/drm/i915/intel_atomic_plane.c |  20 ++
>  drivers/gpu/drm/i915/intel_bw.c           | 190 ++++++++++++
>  drivers/gpu/drm/i915/intel_display.c      |  39 ++-
>  drivers/gpu/drm/i915/intel_drv.h          |  32 ++
>  7 files changed, 637 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_bw.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 68fecf355471..2d24bdd501c4 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -126,6 +126,7 @@ i915-y += intel_audio.o \
>  	  intel_atomic.o \
>  	  intel_atomic_plane.o \
>  	  intel_bios.o \
> +	  intel_bw.o \
>  	  intel_cdclk.o \
>  	  intel_color.o \
>  	  intel_combo_phy.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 8b37ec0e0676..134d1b1a93f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1451,6 +1451,348 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> +#define  SKL_QCLK_RATIO_MASK (0x7f << 0)
> +#define  SKL_QCLK_RATIO_SHIT 0
> +#define  SKL_QCLK_REFERENCE (1 << 7)
> +#define  CNL_QCLK_RATIO_MASK (0x7f << 2)
> +#define  CNL_QCLK_RATIO_SHIT 2
> +#define  CNL_QCLK_REFERENCE (1 << 9)
> +#define  ICL_QCLK_RATIO_MASK (0xff << 2)
> +#define  ICL_QCLK_RATIO_SHIT 2
> +#define  ICL_QCLK_REFERENCE (1 << 10)
> +
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
> +#define MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4400)
> +#define  SKL_DRAM_T_WRPRE_MASK (0x7f << 24)
> +#define  SKL_DRAM_T_WRPRE_SHIFT 24
> +#define  SKL_DRAM_T_RDPRE_MASK (0xf << 16)
> +#define  SKL_DRAM_T_RDPRE_SHIFT 16
> +#define  SKL_DRAM_T_RAS_MASK (0x7f << 8)
> +#define  SKL_DRAM_T_RAS_SHIFT 8
> +#define  SKL_DRAM_T_RPAB_EXT_MASK (0x3 << 6)
> +#define  SKL_DRAM_T_RPAB_EXT_SHIFT 6
> +#define  SKL_DRAM_T_RP_MASK (0x3f << 0)
> +#define  SKL_DRAM_T_RP_SHIFT 0
> +#define  CNL_DRAM_T_WRPRE_MASK (0xff << 24)
> +#define  CNL_DRAM_T_WRPRE_SHIFT 24
> +#define  CNL_DRAM_T_PPD_MASK (0x7 << 21)
> +#define  CNL_DRAM_T_PPD_SHIFT 21
> +#define  CNL_DRAM_T_RDPRE_MASK (0x1f << 16)
> +#define  CNL_DRAM_T_RDPRE_SHIFT 16
> +#define  CNL_DRAM_T_RAS_MASK (0x7f << 9)
> +#define  CNL_DRAM_T_RAS_SHIFT 9
> +#define  CNL_DRAM_T_RPAB_EXT_MASK (0x7 << 6)
> +#define  CNL_DRAM_T_RPAB_EXT_SHIFT 6
> +#define  CNL_DRAM_T_RP_MASK (0x3f << 0)
> +#define  CNL_DRAM_T_RP_SHIFT 0
> +
> +struct intel_dram_timings {
> +	u8 t_rp, t_rdpre, t_ras, t_bl;
> +};
> +
> +static int icl_get_dclk(struct drm_i915_private *dev_priv)
> +{
> +	int ratio, ref;
> +	u32 val;
> +
> +	val = I915_READ(SA_PERF_STATUS_0_0_0_MCHBAR_PC);
> +
> +	DRM_DEBUG_KMS("SA_PERF = 0x%x\n", val);
> +	DRM_DEBUG_KMS("BIOS_DATA = 0x%x\n",
> +		      I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU));
> +
> +	ratio = (val & ICL_QCLK_RATIO_MASK) >> ICL_QCLK_RATIO_SHIT;
> +
> +	if (val & ICL_QCLK_REFERENCE)
> +		ref = 6; /* 6 * 16.666 MHz = 100 MHz */
> +	else
> +		ref = 8; /* 8 * 16.666 MHz = 133 MHz */
> +
> +	return ratio * ref;
> +}
> +
> +#if 0
> +static void skl_get_dram_ch_timings(struct intel_dram_timings *t,
> +				    int channel, enum intel_dram_type type,
> +				    u32 val)
> +{
> +	t->t_rp = (val & SKL_DRAM_T_RP_MASK) >> SKL_DRAM_T_RP_SHIFT;
> +	t->t_rdpre = (val & SKL_DRAM_T_RDPRE_MASK) >> SKL_DRAM_T_RDPRE_SHIFT;
> +	t->t_ras = (val & SKL_DRAM_T_RAS_MASK) >> SKL_DRAM_T_RAS_SHIFT;
> +	t->t_bl = type == INTEL_DRAM_DDR4 ? 4 : 8;
> +
> +	DRM_DEBUG_KMS("CH%d tRP=%d tRDPRE=%d tRAS=%d tBL=%d\n",
> +		      channel, t->t_rp, t->t_rdpre, t->t_ras, t->t_bl);
> +}
> +
> +static void skl_get_dram_timings(struct drm_i915_private *dev_priv,
> +				 const struct dram_info *dram,
> +				 struct intel_dram_timings *t)
> +{
> +	if (dram->channels & BIT(0)) {
> +		u32 val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> +
> +		skl_get_dram_ch_timings(t, 0, dram->type, val);
> +	} else if (dram->channels & BIT(1)) {
> +		u32 val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
> +
> +		skl_get_dram_ch_timings(t, 1, dram->type, val);
> +	}
> +}
> +#endif
> +
> +static void cnl_get_dram_ch_timings(struct intel_dram_timings *t,
> +				    int channel, enum intel_dram_type type,
> +				    u32 val)
> +{
> +	t->t_rp = (val & CNL_DRAM_T_RP_MASK) >> CNL_DRAM_T_RP_SHIFT;
> +	t->t_rdpre = (val & CNL_DRAM_T_RDPRE_MASK) >> CNL_DRAM_T_RDPRE_SHIFT;
> +	t->t_ras = (val & CNL_DRAM_T_RAS_MASK) >> CNL_DRAM_T_RAS_SHIFT;
> +	t->t_bl = type == INTEL_DRAM_DDR4 ? 4 : 8;
> +
> +	DRM_DEBUG_KMS("CH%d tRP=%d tRDPRE=%d tRAS=%d tBL=%d\n",
> +		      channel, t->t_rp, t->t_rdpre, t->t_ras, t->t_bl);
> +}
> +
> +static void cnl_get_dram_timings(struct drm_i915_private *dev_priv,
> +				 const struct dram_info *dram,
> +				 struct intel_dram_timings *t)
> +{
> +	u32 val;
> +
> +	if (dram->channels & BIT(0)) {
> +		val = I915_READ(MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> +		cnl_get_dram_ch_timings(t, 0, dram->type, val);
> +	} else if (dram->channels & BIT(1)) {
> +		val = I915_READ(MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR);
> +		cnl_get_dram_ch_timings(t, 1, dram->type, val);
> +	}
> +}
> +
> +struct intel_sagv_point {
> +	u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
> +};
> +
> +struct intel_sagv_info {
> +	struct intel_sagv_point points[3];
> +	int num_points;
> +};
> +
> +static void icl_get_sagv_points(struct drm_i915_private *dev_priv,
> +				struct intel_sagv_info *si,
> +				const struct intel_dram_timings *t)
> +{
> +	int dclk, i;
> +
> +	dclk = icl_get_dclk(dev_priv);
> +
> +	si->num_points = 3;
> +
> +	/*
> +	 * ICL Hardcoded
> +	 * Name  Description         MC clock(MHz)     DDR data rate(MT / s)  Gear
> +	 * Low   Min voltage point   1066              2133                   2
> +	 * Med   Max DDR rate point  Max DDR freq / 2  Max DDR freq           2
> +	 * High  Min latency point   2667              Same as MC clock       1
> +	 */
> +	si->points[0].dclk = min(64, dclk);
> +	si->points[1].dclk = dclk;
> +	si->points[2].dclk = min(80, dclk);
> +
> +	for (i = 0; i < si->num_points; i++) {
> +		struct intel_sagv_point *sp = &si->points[i];
> +
> +		/*
> +		 * We assume these scale linearly.
> +		 * Seems to match observed behaviour.
> +		 */
> +		sp->t_rp = DIV_ROUND_UP(t->t_rp * sp->dclk, dclk);
> +		sp->t_rdpre = DIV_ROUND_UP(t->t_rdpre * sp->dclk, dclk);
> +		sp->t_ras = DIV_ROUND_UP(t->t_ras * sp->dclk, dclk);
> +
> +		sp->t_rcd = sp->t_rp;
> +		sp->t_rc = sp->t_rp + sp->t_ras;
> +
> +		DRM_DEBUG_KMS("SAGV %d DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
> +			      i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
> +			      sp->t_rcd, sp->t_rc);
> +	}
> +}
> +
> +static int icl_calc_bw(int dclk, int num, int den)
> +{
> +	/* multiples of 2 x 16.666MHz (100/6) */
> +	return DIV_ROUND_CLOSEST(num * dclk * 2 * 100, den * 6);
> +}
> +
> +static int icl_sagv_max_dclk(const struct intel_sagv_info *si)
> +{
> +	u16 dclk = 0;
> +	int i;
> +
> +	for (i = 0; i < si->num_points; i++)
> +		dclk = max(dclk, si->points[i].dclk);
> +
> +	return dclk;
> +}
> +
> +struct intel_sa_info {
> +	u8 deburst, mpagesize, deprogbwlimit, displayrtids;
> +};
> +
> +static const struct intel_sa_info icl_sa_info = {
> +	.deburst = 8,
> +	.mpagesize = 16,
> +	.deprogbwlimit = 25, /* GB/s */
> +	.displayrtids = 128,
> +};
> +
> +static void icl_get_bw_info(struct drm_i915_private *dev_priv)
> +{
> +	const struct dram_info *dram = &dev_priv->dram_info;
> +	struct intel_sagv_info si = {};
> +	struct intel_dram_timings t = {};
> +	const struct intel_sa_info *sa = &icl_sa_info;
> +	bool is_y_tile = true; /* assume y tile may be used */
> +	int num_channels = hweight8(dram->channels);
> +	int deinterleave;
> +#if 0
> +	int clpchpblock;
> +	int pagelimit;
> +#endif
> +	int ipqdepth, ipqdepthpch;
> +	int dclk_max;
> +	int maxdebw;
> +	int i;
> +
> +	/*
> +	 * Try to muzzle SAGV to prevent it from
> +	 * messing up the memory controller readout.
> +	 */
> +	intel_disable_sagv(dev_priv);
> +
> +	/*
> +	 * Magic sleep to avoid observing very high DDR clock.
> +	 * Not sure what's going on but on a system with DDR4-3200
> +	 * clock of 4800 MT/s is often observed here. A short
> +	 * sleep manages to hide that.. Is that actually
> +	 * the "min latency" SAGV point?. Maybe the SA clocks
> +	 * things way up when there is no memory traffic?
> +	 * But polling the register never seems to show this
> +	 * except during i915 unload/load. Sleeping before the
> +	 * SAGV disable usually returns 2133 MT/s.
> +	 *
> +	 * FIXME what is going on?
> +	 */
> +	msleep(5);
> +
> +	cnl_get_dram_timings(dev_priv, dram, &t);
> +
> +	icl_get_sagv_points(dev_priv, &si, &t);
> +
> +	deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> +	dclk_max = icl_sagv_max_dclk(&si);
> +
> +	ipqdepthpch = 16;
> +
> +	maxdebw = min(sa->deprogbwlimit * 1000,
> +		      icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */
> +#if 0
> +	clpchpblock = deinterleave * 8 / num_channels;
> +	pagelimit = sa->mpagesize * deinterleave * 2 / num_channels;
> +#endif
> +	ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +
> +	DRM_DEBUG_KMS("maxdebw = %d\n", maxdebw);
> +	DRM_DEBUG_KMS("ipqdepth = %d\n", ipqdepth);
> +	DRM_DEBUG_KMS("deinterleave = %d\n", deinterleave);
> +	DRM_DEBUG_KMS("dclk_max = %d\n", dclk_max);
> +
> +	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> +		struct intel_bw_info *bi = &dev_priv->max_bw[i];
> +		int clpchgroup;
> +		int j;
> +
> +		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
> +		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
> +
> +		DRM_DEBUG_KMS("clpchgroup = %d\n", clpchgroup);
> +		DRM_DEBUG_KMS("num_planes = %d\n", bi->num_planes);
> +
> +		for (j = 0; j < si.num_points; j++) {
> +			const struct intel_sagv_point *sp = &si.points[j];
> +			int ct, bw;
> +
> +			/*
> +			 * Max row cycle time
> +			 *
> +			 * FIXME what is the logic behind the
> +			 * assumed burst length?
> +			 */
> +			ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
> +				   (clpchgroup - 1) * t.t_bl + sp->t_rdpre);
> +			bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
> +
> +			DRM_DEBUG_KMS("ct = %d\n", ct);
> +			DRM_DEBUG_KMS("bw = %d\n", bw);
> +
> +			bi->deratedbw[j] = min(maxdebw,
> +					       bw * 9 / 10); /* 90% */
> +		}
> +
> +		if (bi->num_planes == 1)
> +			break;
> +	}
> +}
> +
> +static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
> +			       int num_planes, int sagv)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> +		const struct intel_bw_info *bi =
> +			&dev_priv->max_bw[i];
> +
> +		if (num_planes >= bi->num_planes)
> +			return bi->deratedbw[sagv];
> +	}
> +
> +	return 0;
> +}
> +
> +unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> +				 int num_planes)
> +{
> +	if (IS_ICELAKE(dev_priv))
> +		/*
> +		 * FIXME with SAGV disabled maybe we can assume
> +		 * point 1 will always be used? Seems to match
> +		 * the behaviour observed in the wild.
> +		 */
> +		return min3(icl_max_bw(dev_priv, num_planes, 0),
> +			    icl_max_bw(dev_priv, num_planes, 1),
> +			    icl_max_bw(dev_priv, num_planes, 2));
> +	else
> +		return UINT_MAX;
> +}
> +
> +static void icl_dump_max_bw(struct drm_i915_private *dev_priv)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> +		const struct intel_bw_info *bi = &dev_priv->max_bw[i];
> +		int j;
> +
> +		for (j = 0; j < ARRAY_SIZE(bi->deratedbw); j++) {
> +			DRM_DEBUG_KMS("BW%d SAGV%d: num_planes=%d deratedbw=%d\n",
> +				      i, j, bi->num_planes, bi->deratedbw[j]);
> +		}
> +	}
> +}
> +
>  static void
>  intel_get_dram_info(struct drm_i915_private *dev_priv)
>  {
> @@ -1629,6 +1971,10 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_get_dram_info(dev_priv);
>  
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		icl_get_bw_info(dev_priv);
> +		icl_dump_max_bw(dev_priv);
> +	}
>  
>  	return 0;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f638c0c74955..825bea3176fc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -54,6 +54,7 @@
>  #include <drm/drm_cache.h>
>  #include <drm/drm_util.h>
>  #include <drm/drm_dsc.h>
> +#include <drm/drm_atomic.h>
>  #include <drm/drm_connector.h>
>  #include <drm/i915_mei_hdcp_interface.h>
>  
> @@ -1845,6 +1846,13 @@ struct drm_i915_private {
>  		} type;
>  	} dram_info;
>  
> +	struct intel_bw_info {
> +		int num_planes;
> +		int deratedbw[3];
> +	} max_bw[6];
> +
> +	struct drm_private_obj bw_obj;
> +
>  	struct i915_runtime_pm runtime_pm;
>  
>  	struct {
> @@ -2634,6 +2642,8 @@ extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
>  extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
>  extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
>  int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
> +unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> +				 int num_planes);
>  
>  int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
>  int intel_engines_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 9d32a6fcf840..de6b23ee6306 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -111,6 +111,22 @@ intel_plane_destroy_state(struct drm_plane *plane,
>  	drm_atomic_helper_plane_destroy_state(plane, state);
>  }
>  
> +unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> +				   const struct intel_plane_state *plane_state)
> +{
> +	const struct drm_framebuffer *fb = plane_state->base.fb;
> +	unsigned int cpp = 0;
> +	int i;
> +
> +	if (!plane_state->base.visible)
> +		return 0;
> +
> +	for (i = 0; i < fb->format->num_planes; i++)
> +		cpp += fb->format->cpp[i];
> +
> +	return cpp * crtc_state->pixel_rate;

This doesn't take into account plane width/height? Surely that affects bandwidth as well?

This breaks kms_atomic_transition, which tries to decrease plane size to reduce load when max plane width/height is not supported.

According to this calculation, 6 256x256 overlay planes will take the same bandwidth as 6 planes filled with 4k fb's

~Maarten

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Intel-gfx@lists.freedesktop.org
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cf425d8d7a31 drm/i915: Turn dram_info.num_channels into a bitmask
8dd2ae9c334d drm/i915: Make sure we have enough memory bandwidth on ICL
-:115: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#115: FILE: drivers/gpu/drm/i915/i915_drv.c:1515:
+#if 0

-:260: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#260: FILE: drivers/gpu/drm/i915/i915_drv.c:1660:
+#if 0

-:288: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt
#288: FILE: drivers/gpu/drm/i915/i915_drv.c:1688:
+	msleep(5);

-:301: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#301: FILE: drivers/gpu/drm/i915/i915_drv.c:1701:
+#if 0

-:491: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#491: 
new file mode 100644

total: 0 errors, 5 warnings, 0 checks, 771 lines checked

_______________________________________________
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✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_channels into a bitmask
Okay!

Commit: drm/i915: Make sure we have enough memory bandwidth on ICL
+drivers/gpu/drm/i915/i915_drv.c:1599:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1601:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1635:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1635:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1699:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1699:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1705:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1705:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1733:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1733:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1740:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1740:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1774:24: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3559:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

_______________________________________________
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✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask
URL   : https://patchwork.freedesktop.org/series/58299/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5784 -> Patchwork_12537
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12537 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12537, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58299/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12537:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_cpu_reloc@basic:
    - fi-icl-u3:          PASS -> INCOMPLETE

  
Known issues
------------

  Here are the changes found in Patchwork_12537 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] +106

  * igt@kms_busy@basic-flip-a:
    - fi-bsw-n3050:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_busy@basic-flip-c:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-bsw-n3050:       NOTRUN -> SKIP [fdo#109271] +62

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-hsw-peppy:       NOTRUN -> SKIP [fdo#109271] +46

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
    - fi-byt-clapper:     PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         NOTRUN -> FAIL [fdo#103182]

  * igt@runner@aborted:
    - fi-bxt-j4205:       NOTRUN -> FAIL [fdo#109516]

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516


Participating hosts (46 -> 41)
------------------------------

  Additional (3): fi-hsw-peppy fi-gdg-551 fi-bsw-n3050 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-snb-2600 


Build changes
-------------

    * Linux: CI_DRM_5784 -> Patchwork_12537

  CI_DRM_5784: 7f9065d7aaa6abe9bc07e3694a8f3e2d5a91eebe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12537: 8dd2ae9c334d4192926b2c08a9429e60429cd10a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8dd2ae9c334d drm/i915: Make sure we have enough memory bandwidth on ICL
cf425d8d7a31 drm/i915: Turn dram_info.num_channels into a bitmask

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12537/
_______________________________________________
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f4885c7c00de drm/i915: Turn dram_info.num_channels into a bitmask
ccea795b7d3c drm/i915: Make sure we have enough memory bandwidth on ICL
-:115: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#115: FILE: drivers/gpu/drm/i915/i915_drv.c:1476:
+#if 0

-:260: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#260: FILE: drivers/gpu/drm/i915/i915_drv.c:1621:
+#if 0

-:288: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt
#288: FILE: drivers/gpu/drm/i915/i915_drv.c:1649:
+	msleep(5);

-:301: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#301: FILE: drivers/gpu/drm/i915/i915_drv.c:1662:
+#if 0

-:491: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#491: 
new file mode 100644

total: 0 errors, 5 warnings, 0 checks, 771 lines checked

_______________________________________________
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✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_channels into a bitmask
Okay!

Commit: drm/i915: Make sure we have enough memory bandwidth on ICL
+drivers/gpu/drm/i915/i915_drv.c:1560:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1562:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1596:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1596:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1660:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1660:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1666:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1666:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1694:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1694:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1701:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1701:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3562:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

_______________________________________________
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✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2)
URL   : https://patchwork.freedesktop.org/series/58299/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12539
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12539 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12539, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58299/revisions/2/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12539:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_uncore:
    - fi-skl-gvtdvm:      PASS -> DMESG-FAIL

  
Known issues
------------

  Here are the changes found in Patchwork_12539 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-bsw-kefka:       PASS -> FAIL [fdo#100368]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362] +2

  * igt@runner@aborted:
    - fi-bxt-j4205:       NOTRUN -> FAIL [fdo#109516]
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#109373]

  
#### Possible fixes ####

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         FAIL [fdo#104008] -> PASS

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516


Participating hosts (47 -> 38)
------------------------------

  Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5785 -> Patchwork_12539

  CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12539: ccea795b7d3c988c224a62d0e3b660817be5079c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ccea795b7d3c drm/i915: Make sure we have enough memory bandwidth on ICL
f4885c7c00de drm/i915: Turn dram_info.num_channels into a bitmask

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12539/
_______________________________________________
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
77f4b2fd475a drm/i915: Turn dram_info.num_channels into a bitmask
155ce7c67249 drm/i915: Make sure we have enough memory bandwidth on ICL
-:115: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#115: FILE: drivers/gpu/drm/i915/i915_drv.c:1476:
+#if 0

-:260: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#260: FILE: drivers/gpu/drm/i915/i915_drv.c:1621:
+#if 0

-:288: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt
#288: FILE: drivers/gpu/drm/i915/i915_drv.c:1649:
+	msleep(5);

-:301: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#301: FILE: drivers/gpu/drm/i915/i915_drv.c:1662:
+#if 0

-:491: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#491: 
new file mode 100644

total: 0 errors, 5 warnings, 0 checks, 771 lines checked

_______________________________________________
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✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)
URL   : https://patchwork.freedesktop.org/series/58299/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Turn dram_info.num_channels into a bitmask
Okay!

Commit: drm/i915: Make sure we have enough memory bandwidth on ICL
+drivers/gpu/drm/i915/i915_drv.c:1560:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1562:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1596:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1596:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1660:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1660:19: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1666:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1666:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1694:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1694:30: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1701:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1701:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1735:24: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3562:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

_______________________________________________
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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)
URL   : https://patchwork.freedesktop.org/series/58299/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12540
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58299/revisions/3/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12540 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-hsw-4770:        PASS -> SKIP [fdo#109271] +3

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      PASS -> FAIL [fdo#108511]
    - fi-skl-6600u:       PASS -> INCOMPLETE [fdo#107807]

  * igt@i915_selftest@live_evict:
    - fi-bsw-kefka:       PASS -> DMESG-WARN [fdo#107709]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  * igt@runner@aborted:
    - fi-bxt-j4205:       NOTRUN -> FAIL [fdo#109516]
    - fi-bsw-kefka:       NOTRUN -> FAIL [fdo#107709]
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#109373]

  
#### Possible fixes ####

  * igt@kms_busy@basic-flip-b:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         FAIL [fdo#104008] -> PASS

  
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516


Participating hosts (47 -> 38)
------------------------------

  Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5785 -> Patchwork_12540

  CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12540: 155ce7c6724938faf44c0c40a5d77581be26512f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

155ce7c67249 drm/i915: Make sure we have enough memory bandwidth on ICL
77f4b2fd475a drm/i915: Turn dram_info.num_channels into a bitmask

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12540/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)

[Saarinen, Jani]

Finally, now need shards data ;). 

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: torstai 21. maaliskuuta 2019 8.34
> To: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Turn
> dram_info.num_channels into a bitmask (rev3)
> 
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a
> bitmask (rev3)
> URL   : https://patchwork.freedesktop.org/series/58299/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5785 -> Patchwork_12540
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   External URL:
> https://patchwork.freedesktop.org/api/1.0/series/58299/revisions/3/mbox/
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_12540 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_exec_suspend@basic-s4-devices:
>     - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]
> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
>     - fi-hsw-4770:        PASS -> SKIP [fdo#109271] +3
> 
>   * igt@i915_pm_rpm@module-reload:
>     - fi-skl-6770hq:      PASS -> FAIL [fdo#108511]
>     - fi-skl-6600u:       PASS -> INCOMPLETE [fdo#107807]
> 
>   * igt@i915_selftest@live_evict:
>     - fi-bsw-kefka:       PASS -> DMESG-WARN [fdo#107709]
> 
>   * igt@prime_vgem@basic-fence-flip:
>     - fi-gdg-551:         PASS -> FAIL [fdo#103182]
> 
>   * igt@runner@aborted:
>     - fi-bxt-j4205:       NOTRUN -> FAIL [fdo#109516]
>     - fi-bsw-kefka:       NOTRUN -> FAIL [fdo#107709]
>     - fi-apl-guc:         NOTRUN -> FAIL [fdo#109373]
> 
> 
> #### Possible fixes ####
> 
>   * igt@kms_busy@basic-flip-b:
>     - fi-gdg-551:         FAIL [fdo#103182] -> PASS
> 
>   * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
>     - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS
> 
>   * igt@prime_vgem@basic-fence-flip:
>     - fi-ilk-650:         FAIL [fdo#104008] -> PASS
> 
> 
>   [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
>   [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
>   [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
>   [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
>   [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
>   [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
>   [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
>   [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
>   [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
> 
> 
> Participating hosts (47 -> 38)
> ------------------------------
> 
>   Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-
> bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus
> 
> 
> Build changes
> -------------
> 
>     * Linux: CI_DRM_5785 -> Patchwork_12540
> 
>   CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_12540: 155ce7c6724938faf44c0c40a5d77581be26512f @
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 155ce7c67249 drm/i915: Make sure we have enough memory bandwidth on ICL
> 77f4b2fd475a drm/i915: Turn dram_info.num_channels into a bitmask
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12540/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3)
URL   : https://patchwork.freedesktop.org/series/58299/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5785_full -> Patchwork_12540_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12540_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12540_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12540_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-hsw:          PASS -> FAIL

  * igt@kms_atomic_transition@plane-all-transition:
    - shard-iclb:         NOTRUN -> FAIL

  * igt@kms_properties@connector-properties-atomic:
    - shard-iclb:         PASS -> FAIL +2

  
Known issues
------------

  Here are the changes found in Patchwork_12540_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_param@invalid-param-get:
    - shard-skl:          NOTRUN -> FAIL [fdo#109559]

  * igt@gem_ctx_param@invalid-param-set:
    - shard-hsw:          NOTRUN -> FAIL [fdo#109674]

  * igt@gem_eio@reset-stress:
    - shard-snb:          PASS -> FAIL [fdo#109661]

  * igt@gem_exec_schedule@deep-bsd:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +43

  * igt@gem_pwrite@stolen-normal:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +37

  * igt@gem_softpin@evict-snoop:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109312]

  * igt@gem_tiled_swapping@non-threaded:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#108686]

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109301]

  * igt@i915_pm_rpm@universal-planes:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#107956]
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-snb:          PASS -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_busy@extended-pageflip-hang-newfb-render-d:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
    - shard-kbl:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_chamelium@hdmi-cmp-yv16:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +96

  * igt@kms_cursor_crc@cursor-512x512-dpms:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109279]

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          PASS -> FAIL [fdo#105767]

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-iclb:         PASS -> FAIL [fdo#103355] +1

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +2

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
    - shard-skl:          PASS -> FAIL [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-snb:          PASS -> SKIP [fdo#109271] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +12

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +2

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] +23

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +7

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#105682] / [fdo#109247]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109247] +2

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-f:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +1

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-skl:          PASS -> INCOMPLETE [fdo#104108]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_scaling@pipe-c-plane-scaling:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109052]

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +2

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109441]

  * igt@kms_psr@sprite_mmap_cpu:
    - shard-iclb:         PASS -> FAIL [fdo#107383] / [fdo#110215] +2

  * igt@kms_psr@sprite_render:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107383] / [fdo#110215] +1

  * igt@kms_rmfb@rmfb-ioctl:
    - shard-iclb:         PASS -> FAIL [fdo#109052]

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          PASS -> INCOMPLETE [fdo#103665]

  * igt@kms_setmode@basic:
    - shard-skl:          NOTRUN -> FAIL [fdo#99912]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9

  * igt@prime_vgem@fence-wait-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +2

  * igt@runner@aborted:
    - shard-apl:          NOTRUN -> ( 36 FAIL ) [fdo#109373]

  
#### Possible fixes ####

  * igt@gem_create@create-clear:
    - shard-snb:          INCOMPLETE [fdo#105411] -> PASS +1

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-iclb:         TIMEOUT [fdo#109673] -> PASS

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +4

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +19

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] -> PASS

  * igt@kms_psr@primary_mmap_cpu:
    - shard-iclb:         FAIL [fdo#107383] / [fdo#110215] -> PASS +2

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          FAIL [fdo#109016] -> PASS

  * igt@kms_setmode@basic:
    - shard-kbl:          FAIL [fdo#99912] -> PASS

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-iclb:         FAIL [fdo#104894] -> PASS

  
#### Warnings ####

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          INCOMPLETE [fdo#107773] -> FAIL [fdo#107847]

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         SKIP [fdo#109349] -> FAIL [fdo#109358]

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         SKIP [fdo#109441] -> FAIL [fdo#107383] / [fdo#110215] +1

  * igt@runner@aborted:
    - shard-glk:          FAIL [fdo#109373] / [k.org#202321] -> ( 36 FAIL ) [k.org#202321]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109358]: https://bugs.freedesktop.org/show_bug.cgi?id=109358
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
  [fdo#110034]: https://bugs.freedesktop.org/show_bug.cgi?id=110034
  [fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5785 -> Patchwork_12540

  CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12540: 155ce7c6724938faf44c0c40a5d77581be26512f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12540/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx