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From: David Miller <davem@davemloft.net>
To: hkallweit1@gmail.com
Cc: andrew@lunn.ch, f.fainelli@gmail.com, netdev@vger.kernel.org,
	preid@electromag.com.au, liweihang@hisilicon.com
Subject: Re: [PATCH net] net: phy: don't clear BMCR in genphy_soft_reset
Date: Mon, 25 Mar 2019 17:09:29 -0700 (PDT)	[thread overview]
Message-ID: <20190325.170929.2240397133766757467.davem@davemloft.net> (raw)
In-Reply-To: <58079905-c107-6b41-ce04-3d88ef00d70b@gmail.com>

From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Fri, 22 Mar 2019 20:00:20 +0100

> So far we effectively clear the BMCR register. Some PHY's can deal
> with this (e.g. because they reset BMCR to a default as part of a
> soft-reset) whilst on others this causes issues because e.g. the
> autoneg bit is cleared. Marvell is an example, see also thread [0].
> So let's be a little bit more gentle and leave all bits we're not
> interested in as-is. This change is needed for PHY drivers to
> properly deal with the original patch.
> 
> [0] https://marc.info/?t=155264050700001&r=1&w=2
> 
> Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset")
> Tested-by: Phil Reid <preid@electromag.com.au>
> Tested-by: liweihang <liweihang@hisilicon.com>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

Applied and queued up for -stable, thanks.

      parent reply	other threads:[~2019-03-26  0:13 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22 19:00 [PATCH net] net: phy: don't clear BMCR in genphy_soft_reset Heiner Kallweit
2019-03-24  0:59 ` Florian Fainelli
2019-03-26  0:09 ` David Miller [this message]

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