From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcel Ziswiler Date: Mon, 25 Mar 2019 17:25:11 +0100 Subject: [U-Boot] [PATCH v2 21/22] colibri_vf: use leveling evaluated by DDR validation tools In-Reply-To: <20190325162512.8702-1-marcel@ziswiler.com> References: <20190325162512.8702-1-marcel@ziswiler.com> Message-ID: <20190325162512.8702-22-marcel@ziswiler.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Stefan Agner The DDR validation tool (which is part of Processor Expert) allows to evaluate leveling parameters for CR105/CR106/CR110. Several runs have been made with Colibri VF50 and VF61 and it seems to evaluate very similar values. Use this values by default. Note: The newly evaluated parameters seem to require CTLUPD_AREF to be enabled! Note 2: The tool also evaluated 6 as a new value for PHY02/18 GATE_CFG (Coarse adjust of gate open time). However, this seems not to work in practise. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- Changes in v2: None board/toradex/colibri_vf/colibri_vf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 3e39912f91..9d63fbf3bd 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -29,6 +29,13 @@ DECLARE_GLOBAL_DATA_PTR; #define PTC0_GPIO_45 45 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + { DDRMC_CR79_CTLUPD_AREF(1), 79 }, + /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ + { DDRMC_CR105_RDLVL_DL_0(28), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, + { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, + { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, + /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, -- 2.20.1