All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: suzuki.poulose@arm.com, alexander.shishkin@linux.intel.com,
	coresight@lists.linaro.org, peterz@infradead.org,
	mike.leach@arm.com, leo.yan@linaro.org
Subject: [PATCH v2 16/16] coresight: etb10: Add support for CPU-wide trace scenarios
Date: Mon, 25 Mar 2019 15:56:32 -0600	[thread overview]
Message-ID: <20190325215632.17013-17-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190325215632.17013-1-mathieu.poirier@linaro.org>

This patch adds support for CPU-wide trace scenarios by making sure that
only the sources monitoring the same process have access to a common sink.
Because the sink is shared between sources, the first source to use the
sink switches it on while the last one does the cleanup.  Any attempt to
modify the HW is overlooked for as long as more than one source is using
a sink.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etb10.c | 43 +++++++++++++++++--
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 7d64c41cd8ac..a2379c00d635 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -72,6 +72,8 @@
  * @miscdev:	specifics to handle "/dev/xyz.etb" entry.
  * @spinlock:	only one at a time pls.
  * @reading:	synchronise user space access to etb buffer.
+ * @pid:	Process ID of the process being monitored by the session
+ *		that is using this component.
  * @buf:	area of memory where ETB buffer content gets sent.
  * @mode:	this ETB is being used.
  * @buffer_depth: size of @buf.
@@ -85,6 +87,7 @@ struct etb_drvdata {
 	struct miscdevice	miscdev;
 	spinlock_t		spinlock;
 	local_t			reading;
+	pid_t			pid;
 	u8			*buf;
 	u32			mode;
 	u32			buffer_depth;
@@ -177,28 +180,49 @@ static int etb_enable_sysfs(struct coresight_device *csdev)
 static int etb_enable_perf(struct coresight_device *csdev, void *data)
 {
 	int ret = 0;
+	pid_t pid;
 	unsigned long flags;
 	struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+	struct perf_output_handle *handle = data;
 
 	spin_lock_irqsave(&drvdata->spinlock, flags);
 
-	/* No need to continue if the component is already in use. */
-	if (drvdata->mode != CS_MODE_DISABLED) {
+	/* No need to continue if the component is already in used by sysFS. */
+	if (drvdata->mode == CS_MODE_SYSFS) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/* Get a handle on the pid of the process to monitor */
+	pid = task_pid_nr(handle->event->owner);
+
+	if (drvdata->pid != -1 && drvdata->pid != pid) {
 		ret = -EBUSY;
 		goto out;
 	}
 
+	/*
+	 * No HW configuration is needed if the sink is already in
+	 * use for this session.
+	 */
+	if (drvdata->pid == pid) {
+		atomic_inc(csdev->refcnt);
+		goto out;
+	}
+
 	/*
 	 * We don't have an internal state to clean up if we fail to setup
 	 * the perf buffer. So we can perform the step before we turn the
 	 * ETB on and leave without cleaning up.
 	 */
-	ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
+	ret = etb_set_buffer(csdev, handle);
 	if (ret)
 		goto out;
 
 	ret = etb_enable_hw(drvdata);
 	if (!ret) {
+		/* Associate with monitored process. */
+		drvdata->pid = pid;
 		drvdata->mode = CS_MODE_PERF;
 		atomic_inc(csdev->refcnt);
 	}
@@ -344,6 +368,8 @@ static int etb_disable(struct coresight_device *csdev)
 	/* Complain if we (somehow) got out of sync */
 	WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED);
 	etb_disable_hw(drvdata);
+	/* Dissociate from monitored process. */
+	drvdata->pid = -1;
 	drvdata->mode = CS_MODE_DISABLED;
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
@@ -414,7 +440,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
 	const u32 *barrier;
 	u32 read_ptr, write_ptr, capacity;
 	u32 status, read_data;
-	unsigned long offset, to_read, flags;
+	unsigned long offset, to_read = 0, flags;
 	struct cs_buffers *buf = sink_config;
 	struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 
@@ -424,6 +450,11 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
 	capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
 
 	spin_lock_irqsave(&drvdata->spinlock, flags);
+
+	/* Don't do anything if another tracer is using this sink */
+	if (atomic_read(csdev->refcnt) != 1)
+		goto out;
+
 	__etb_disable_hw(drvdata);
 	CS_UNLOCK(drvdata->base);
 
@@ -534,6 +565,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
 	}
 	__etb_enable_hw(drvdata);
 	CS_LOCK(drvdata->base);
+out:
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
 	return to_read;
@@ -742,6 +774,9 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 	if (!drvdata->buf)
 		return -ENOMEM;
 
+	/* This device is not associated with a session */
+	drvdata->pid = -1;
+
 	desc.type = CORESIGHT_DEV_TYPE_SINK;
 	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 	desc.ops = &etb_cs_ops;
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-03-25 22:07 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25 21:56 [PATCH v2 00/16] coresight: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 01/16] coresight: pmu: Adding ITRACE property to cs_etm PMU Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 02/16] coresight: etm4x: Add kernel configuration for CONTEXTID Mathieu Poirier
2019-03-26 11:59   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 03/16] coresight: etm4x: Configure tracers to emit timestamps Mathieu Poirier
2019-03-26 11:53   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 04/16] coresight: Adding return code to sink::disable() operation Mathieu Poirier
2019-03-26 14:55   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 05/16] coresight: Move reference counting inside sink drivers Mathieu Poirier
2019-03-26 15:04   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 06/16] coresight: Properly address errors in sink::disable() functions Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 07/16] coresight: Properly address concurrency in sink::update() functions Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 08/16] coresight: perf: Clean up function etm_setup_aux() Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 09/16] coresight: perf: Refactor function free_event_data() Mathieu Poirier
2019-03-26 15:07   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 10/16] coresight: Communicate perf event to sink buffer allocation function Mathieu Poirier
2019-03-26 15:12   ` Suzuki K Poulose
2019-03-25 21:56 ` [PATCH v2 11/16] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Mathieu Poirier
2019-03-26 15:29   ` Suzuki K Poulose
2019-03-26 16:29     ` Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 12/16] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Mathieu Poirier
2019-03-26 16:46   ` Suzuki K Poulose
2019-03-26 18:06     ` Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 13/16] coresight: tmc-etr: Allow events to use the same ETR buffer Mathieu Poirier
2019-03-26 16:18   ` Suzuki K Poulose
2019-03-26 17:55     ` Mathieu Poirier
2019-03-27 11:32       ` Suzuki K Poulose
2019-03-27 17:01         ` Mathieu Poirier
2019-04-01 13:01           ` Suzuki K Poulose
2019-04-03  2:13             ` Mathieu Poirier
2019-03-30 15:43   ` Leo Yan
2019-04-01  7:29     ` Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 14/16] coresight: tmc-etr: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-03-25 21:56 ` [PATCH v2 15/16] coresight: tmc-etf: " Mathieu Poirier
2019-03-25 21:56 ` Mathieu Poirier [this message]
2019-03-27  7:52 ` [PATCH v2 00/16] coresight: " Leo Yan
2019-03-27 14:40   ` Mathieu Poirier
2019-03-27 14:44     ` Leo Yan
2019-04-11 18:52 ` Robert Walker
2019-04-16 19:37   ` Mathieu Poirier
2019-04-24 16:22     ` Robert Walker

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190325215632.17013-17-mathieu.poirier@linaro.org \
    --to=mathieu.poirier@linaro.org \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=coresight@lists.linaro.org \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=mike.leach@arm.com \
    --cc=peterz@infradead.org \
    --cc=suzuki.poulose@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.