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* [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
@ 2019-02-26  6:59 Bjorn Andersson
  2019-02-27  9:27 ` Marc Gonzalez
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Bjorn Andersson @ 2019-02-26  6:59 UTC (permalink / raw)
  To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland
  Cc: linux-arm-msm, linux-kernel, devicetree, Can Guo, Vivek Gautam

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for SDM845.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 .../devicetree/bindings/phy/qcom-qmp-phy.txt  |   7 +
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 160 ++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h           |  12 ++
 3 files changed, 179 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 5d181fc3cc18..dd2725a9d3f7 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -11,6 +11,7 @@ Required properties:
 	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
 	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
 	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
+	       "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845,
 	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
 	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
 	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
@@ -48,6 +49,10 @@ Required properties:
 			"aux", "cfg_ahb", "ref".
 		For "qcom,msm8998-qmp-ufs-phy" must contain:
 			"ref", "ref_aux".
+		For "qcom,sdm845-qmp-usb3-phy" must contain:
+			"aux", "cfg_ahb", "ref", "refgen".
+		For "qcom,sdm845-qmp-usb3-phy" must contain:
+			"aux", "cfg_ahb", "ref", "com_aux".
 		For "qcom,sdm845-qmp-usb3-phy" must contain:
 			"aux", "cfg_ahb", "ref", "com_aux".
 		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
@@ -70,6 +75,8 @@ Required properties:
 		For "qcom,msm8998-qmp-usb3-phy" must contain
 			"phy", "common".
 		For "qcom,msm8998-qmp-ufs-phy": no resets are listed.
+		For "qcom,sdm845-qmp-pcie-phy" must contain:
+			"phy".
 		For "qcom,sdm845-qmp-usb3-phy" must contain:
 			"phy", "common".
 		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 08d6f6f7f039..c5ca4a217439 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -159,6 +159,11 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 	[QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 };
 
+static const unsigned int sdm845_pciephy_regs_layout[] = {
+	[QPHY_START_CTRL]		= 0x08,
+	[QPHY_PCS_READY_STATUS]		= 0x174,
+};
+
 static const unsigned int sdm845_ufsphy_regs_layout[] = {
 	[QPHY_START_CTRL]		= 0x00,
 	[QPHY_PCS_READY_STATUS]		= 0x160,
@@ -392,6 +397,109 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 	QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 };
 
+static const struct qmp_phy_init_tbl sdm845_pcie_serdes_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+};
+
+static const struct qmp_phy_init_tbl sdm845_pcie_tx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sdm845_pcie_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+};
+
+static const struct qmp_phy_init_tbl sdm845_pcie_pcs_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
+};
+
+static const struct qmp_phy_init_tbl sdm845_pcie_pcs_misc_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+};
+
 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -813,6 +921,8 @@ struct qmp_phy_cfg {
 	int rx_tbl_num;
 	const struct qmp_phy_init_tbl *pcs_tbl;
 	int pcs_tbl_num;
+	const struct qmp_phy_init_tbl *pcs_misc_tbl;
+	int pcs_misc_tbl_num;
 
 	/* clock ids to be requested */
 	const char * const *clk_list;
@@ -949,6 +1059,10 @@ static const char * const qmp_v3_phy_clk_l[] = {
 	"aux", "cfg_ahb", "ref", "com_aux",
 };
 
+static const char * const sdm845_pciephy_clk_l[] = {
+	"aux", "cfg_ahb", "ref", "refgen",
+};
+
 static const char * const sdm845_ufs_phy_clk_l[] = {
 	"ref", "ref_aux",
 };
@@ -962,6 +1076,10 @@ static const char * const msm8996_usb3phy_reset_l[] = {
 	"phy", "common",
 };
 
+static const char * const sdm845_pciephy_reset_l[] = {
+	"phy",
+};
+
 /* list of regulators */
 static const char * const qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll",
@@ -1059,6 +1177,39 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 	.pwrdn_delay_max	= 1005,		/* us */
 };
 
+static const struct qmp_phy_cfg sdm845_pciephy_cfg = {
+	.type = PHY_TYPE_PCIE,
+	.nlanes = 1,
+
+	.serdes_tbl		= sdm845_pcie_serdes_tbl,
+	.serdes_tbl_num		= ARRAY_SIZE(sdm845_pcie_serdes_tbl),
+	.tx_tbl			= sdm845_pcie_tx_tbl,
+	.tx_tbl_num		= ARRAY_SIZE(sdm845_pcie_tx_tbl),
+	.rx_tbl			= sdm845_pcie_rx_tbl,
+	.rx_tbl_num		= ARRAY_SIZE(sdm845_pcie_rx_tbl),
+	.pcs_tbl		= sdm845_pcie_pcs_tbl,
+	.pcs_tbl_num		= ARRAY_SIZE(sdm845_pcie_pcs_tbl),
+	.pcs_misc_tbl		= sdm845_pcie_pcs_misc_tbl,
+	.pcs_misc_tbl_num	= ARRAY_SIZE(sdm845_pcie_pcs_misc_tbl),
+	.clk_list		= sdm845_pciephy_clk_l,
+	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),
+	.reset_list		= sdm845_pciephy_reset_l,
+	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.regs			= sdm845_pciephy_regs_layout,
+
+	.start_ctrl		= PCS_START | SERDES_START,
+	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
+	.mask_com_pcs_ready	= PCS_READY,
+
+	.has_phy_com_ctrl	= false,
+	.has_lane_rst		= false,
+	.has_pwrdn_delay	= true,
+	.pwrdn_delay_min	= 995,		/* us */
+	.pwrdn_delay_max	= 1005,		/* us */
+};
+
 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
 	.type			= PHY_TYPE_USB3,
 	.nlanes			= 1,
@@ -1344,6 +1495,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
 	void __iomem *tx = qphy->tx;
 	void __iomem *rx = qphy->rx;
 	void __iomem *pcs = qphy->pcs;
+	void __iomem *pcs_misc = qphy->pcs_misc;
 	void __iomem *dp_com = qmp->dp_com;
 	void __iomem *status;
 	unsigned int mask, val;
@@ -1384,6 +1536,11 @@ static int qcom_qmp_phy_init(struct phy *phy)
 
 	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
 
+	if (cfg->pcs_misc_tbl) {
+		qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
+				       cfg->pcs_misc_tbl_num);
+	}
+
 	/*
 	 * UFS PHY requires the deassert of software reset before serdes start.
 	 * For UFS PHYs that do not have software reset control bits, defer
@@ -1878,6 +2035,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
 	}, {
 		.compatible = "qcom,ipq8074-qmp-pcie-phy",
 		.data = &ipq8074_pciephy_cfg,
+	}, {
+		.compatible = "qcom,sdm845-qmp-pcie-phy",
+		.data = &sdm845_pciephy_cfg,
 	}, {
 		.compatible = "qcom,sdm845-qmp-usb3-phy",
 		.data = &qmp_v3_usb3phy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index a1b6cdee9a08..335ea5d7ef40 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -241,6 +241,7 @@
 #define QSERDES_V3_RX_RX_BAND				0x110
 #define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c
 #define QSERDES_V3_RX_RX_MODE_00			0x164
+#define QSERDES_V3_RX_RX_MODE_01			0x168
 
 /* Only for QMP V3 PHY - PCS registers */
 #define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
@@ -280,6 +281,7 @@
 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME			0x08c
 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0
 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8
 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK		0x0b0
 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME		0x0b8
 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME		0x0bc
@@ -292,13 +294,23 @@
 #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME			0x138
 #define QPHY_V3_PCS_RX_SIGDET_CTRL1			0x13c
 #define QPHY_V3_PCS_RX_SIGDET_CTRL2			0x140
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1a8
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS			0x1ac
+#define QPHY_V3_PCS_SIGDET_CNTRL			0x1b0
 #define QPHY_V3_PCS_TX_MID_TERM_CTRL1			0x1bc
 #define QPHY_V3_PCS_MULTI_LANE_CTRL1			0x1c4
 #define QPHY_V3_PCS_RX_SIGDET_LVL			0x1d8
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB	0x1dc
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1e0
 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1			0x20c
 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2			0x210
 
 /* Only for QMP V3 PHY - PCS_MISC registers */
 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE			0x0c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2		0x2c
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1	0x44
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2		0x54
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4		0x5c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5		0x60
 
 #endif
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
@ 2019-02-27  9:27 ` Marc Gonzalez
  2019-02-27 18:09   ` Bjorn Andersson
  2019-02-27 13:48 ` Marc Gonzalez
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 9+ messages in thread
From: Marc Gonzalez @ 2019-02-27  9:27 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, MSM, LKML,
	Can Guo, Vivek Gautam, Jeffrey Hugo, Nicolas Dechesne

On 26/02/2019 07:59, Bjorn Andersson wrote:

> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt  |   7 +
>  drivers/phy/qualcomm/phy-qcom-qmp.c           | 160 ++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h           |  12 ++
>  3 files changed, 179 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> index 5d181fc3cc18..dd2725a9d3f7 100644
> --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -11,6 +11,7 @@ Required properties:
>  	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
>  	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
>  	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
> +	       "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845,
>  	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
>  	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
>  	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
> @@ -48,6 +49,10 @@ Required properties:
>  			"aux", "cfg_ahb", "ref".
>  		For "qcom,msm8998-qmp-ufs-phy" must contain:
>  			"ref", "ref_aux".
> +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> +			"aux", "cfg_ahb", "ref", "refgen".

qcom,sdm845-qmp-usb3-phy in a PCIe patch?

> +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> +			"aux", "cfg_ahb", "ref", "com_aux".

qcom,sdm845-qmp-usb3-phy again in a PCIe patch?


> +static const struct qmp_phy_init_tbl sdm845_pcie_pcs_misc_tbl[] = {
> +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> +};

I was thinking I might need to do the same for msm8998, since downstream
tweaks pcs_misc + 0x2c = 0x52
(dunno if that's QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2)

The thing is, phy driver writes unconditionally to pcs_misc + 0x0c
(QPHY_V3_PCS_MISC_CLAMP_ENABLE). Should that be moved elsewhere?

Regards.

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
  2019-02-27  9:27 ` Marc Gonzalez
@ 2019-02-27 13:48 ` Marc Gonzalez
  2019-03-22 13:42 ` Marc Gonzalez
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Marc Gonzalez @ 2019-02-27 13:48 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, MSM, LKML,
	Can Guo, Vivek Gautam, Jeffrey Hugo

On 26/02/2019 07:59, Bjorn Andersson wrote:

> +static const unsigned int sdm845_pciephy_regs_layout[] = {
> +	[QPHY_START_CTRL]		= 0x08,
> +	[QPHY_PCS_READY_STATUS]		= 0x174,
> +};
> +

Just use pciephy_regs_layout?

> +static const struct qmp_phy_cfg sdm845_pciephy_cfg = {
> +	.type = PHY_TYPE_PCIE,
> +	.nlanes = 1,
> +
> +	.serdes_tbl		= sdm845_pcie_serdes_tbl,
> +	.serdes_tbl_num		= ARRAY_SIZE(sdm845_pcie_serdes_tbl),
> +	.tx_tbl			= sdm845_pcie_tx_tbl,
> +	.tx_tbl_num		= ARRAY_SIZE(sdm845_pcie_tx_tbl),
> +	.rx_tbl			= sdm845_pcie_rx_tbl,
> +	.rx_tbl_num		= ARRAY_SIZE(sdm845_pcie_rx_tbl),
> +	.pcs_tbl		= sdm845_pcie_pcs_tbl,
> +	.pcs_tbl_num		= ARRAY_SIZE(sdm845_pcie_pcs_tbl),
> +	.pcs_misc_tbl		= sdm845_pcie_pcs_misc_tbl,
> +	.pcs_misc_tbl_num	= ARRAY_SIZE(sdm845_pcie_pcs_misc_tbl),
> +	.clk_list		= sdm845_pciephy_clk_l,
> +	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),
> +	.reset_list		= sdm845_pciephy_reset_l,
> +	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
> +	.vreg_list		= qmp_phy_vreg_l,
> +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> +	.regs			= sdm845_pciephy_regs_layout,

pciephy_regs_layout

> +
> +	.start_ctrl		= PCS_START | SERDES_START,
> +	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> +	.mask_com_pcs_ready	= PCS_READY,
> +
> +	.has_phy_com_ctrl	= false,
> +	.has_lane_rst		= false,

Obviously, false entries may be omitted.

> +	.has_pwrdn_delay	= true,
> +	.pwrdn_delay_min	= 995,		/* us */
> +	.pwrdn_delay_max	= 1005,		/* us */

I think you can drop this.

Regards.

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-27  9:27 ` Marc Gonzalez
@ 2019-02-27 18:09   ` Bjorn Andersson
  0 siblings, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2019-02-27 18:09 UTC (permalink / raw)
  To: Marc Gonzalez
  Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, MSM, LKML,
	Can Guo, Vivek Gautam, Jeffrey Hugo, Nicolas Dechesne

On Wed 27 Feb 01:27 PST 2019, Marc Gonzalez wrote:

> On 26/02/2019 07:59, Bjorn Andersson wrote:
> 
> > qcom_qmp_phy_init() is extended to support the additional register
> > writes needed in PCS MISC and the appropriate sequences and resources
> > are defined for SDM845.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >  .../devicetree/bindings/phy/qcom-qmp-phy.txt  |   7 +
> >  drivers/phy/qualcomm/phy-qcom-qmp.c           | 160 ++++++++++++++++++
> >  drivers/phy/qualcomm/phy-qcom-qmp.h           |  12 ++
> >  3 files changed, 179 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> > index 5d181fc3cc18..dd2725a9d3f7 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> > @@ -11,6 +11,7 @@ Required properties:
> >  	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
> >  	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
> >  	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
> > +	       "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845,
> >  	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
> >  	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
> >  	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
> > @@ -48,6 +49,10 @@ Required properties:
> >  			"aux", "cfg_ahb", "ref".
> >  		For "qcom,msm8998-qmp-ufs-phy" must contain:
> >  			"ref", "ref_aux".
> > +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> > +			"aux", "cfg_ahb", "ref", "refgen".
> 
> qcom,sdm845-qmp-usb3-phy in a PCIe patch?
> 

Must have forgotten to fix it up after copy pasting the other line,
thanks for spotting.

> > +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> > +			"aux", "cfg_ahb", "ref", "com_aux".
> 
> qcom,sdm845-qmp-usb3-phy again in a PCIe patch?
> 

Ditto.

> 
> > +static const struct qmp_phy_init_tbl sdm845_pcie_pcs_misc_tbl[] = {
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
> > +	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> > +};
> 
> I was thinking I might need to do the same for msm8998, since downstream
> tweaks pcs_misc + 0x2c = 0x52
> (dunno if that's QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2)
> 

Yeah, we probably should add the 8998 sequences as well. I haven't been
able to compare the two side by side, but it's expected that they will
be slightly different.

> The thing is, phy driver writes unconditionally to pcs_misc + 0x0c
> (QPHY_V3_PCS_MISC_CLAMP_ENABLE). Should that be moved elsewhere?
> 

I spotted this as the only difference in the initialization sequence,
but concluded that it seems to work fine as it is. So I left that part
intact.

Regards,
Bjorn

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
  2019-02-27  9:27 ` Marc Gonzalez
  2019-02-27 13:48 ` Marc Gonzalez
@ 2019-03-22 13:42 ` Marc Gonzalez
  2019-03-29 14:00   ` Marc Gonzalez
  2019-03-22 15:34   ` Evan Green
  2019-03-26 14:59 ` Rob Herring
  4 siblings, 1 reply; 9+ messages in thread
From: Marc Gonzalez @ 2019-03-22 13:42 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, MSM, LKML, Can Guo, Vivek Gautam,
	Evan Green, Jeffrey Hugo

On 26/02/2019 07:59, Bjorn Andersson wrote:

> @@ -1384,6 +1536,11 @@ static int qcom_qmp_phy_init(struct phy *phy)
>  
>  	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
>  
> +	if (cfg->pcs_misc_tbl) {
> +		qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
> +				       cfg->pcs_misc_tbl_num);
> +	}
> +
>  	/*
>  	 * UFS PHY requires the deassert of software reset before serdes start.
>  	 * For UFS PHYs that do not have software reset control bits, defer

I think it would be better to configure pcs_misc *before* pcs.
That would be closer to what downstream does (for 835 and 845 at least).

Also you don't need to test for NULL as that is already done in
qcom_qmp_phy_configure() -- and in fact even that test is redundant,
since the array is not dereferenced when count is 0.

When are you planning on sending a v2 of your PCIe series?

Regards.

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
@ 2019-03-22 15:34   ` Evan Green
  2019-02-27 13:48 ` Marc Gonzalez
                     ` (3 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Evan Green @ 2019-03-22 15:34 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, linux-arm-msm,
	LKML, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Can Guo, Vivek Gautam

On Mon, Feb 25, 2019 at 10:58 PM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---

How badly does this conflict with my refactoring series at [1]? I
believe that series should be just about ready to go, do you want to
base your change on top of it?
-Evan

[1] https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
@ 2019-03-22 15:34   ` Evan Green
  0 siblings, 0 replies; 9+ messages in thread
From: Evan Green @ 2019-03-22 15:34 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, Rob Herring, Mark Rutland, linux-arm-msm,
	LKML, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Can Guo, Vivek Gautam

On Mon, Feb 25, 2019 at 10:58 PM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---

How badly does this conflict with my refactoring series at [1]? I
believe that series should be just about ready to go, do you want to
base your change on top of it?
-Evan

[1] https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
                   ` (3 preceding siblings ...)
  2019-03-22 15:34   ` Evan Green
@ 2019-03-26 14:59 ` Rob Herring
  4 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2019-03-26 14:59 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, Mark Rutland, linux-arm-msm,
	linux-kernel, devicetree, Can Guo, Vivek Gautam

On Mon, Feb 25, 2019 at 10:59:19PM -0800, Bjorn Andersson wrote:
> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt  |   7 +

Please split bindings.

>  drivers/phy/qualcomm/phy-qcom-qmp.c           | 160 ++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h           |  12 ++
>  3 files changed, 179 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> index 5d181fc3cc18..dd2725a9d3f7 100644
> --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -11,6 +11,7 @@ Required properties:
>  	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
>  	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
>  	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
> +	       "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845,
>  	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
>  	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
>  	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
> @@ -48,6 +49,10 @@ Required properties:
>  			"aux", "cfg_ahb", "ref".
>  		For "qcom,msm8998-qmp-ufs-phy" must contain:
>  			"ref", "ref_aux".
> +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> +			"aux", "cfg_ahb", "ref", "refgen".
> +		For "qcom,sdm845-qmp-usb3-phy" must contain:
> +			"aux", "cfg_ahb", "ref", "com_aux".

Copy-n-paste error?

>  		For "qcom,sdm845-qmp-usb3-phy" must contain:
>  			"aux", "cfg_ahb", "ref", "com_aux".
>  		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
> @@ -70,6 +75,8 @@ Required properties:
>  		For "qcom,msm8998-qmp-usb3-phy" must contain
>  			"phy", "common".
>  		For "qcom,msm8998-qmp-ufs-phy": no resets are listed.
> +		For "qcom,sdm845-qmp-pcie-phy" must contain:
> +			"phy".
>  		For "qcom,sdm845-qmp-usb3-phy" must contain:
>  			"phy", "common".
>  		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support
  2019-03-22 13:42 ` Marc Gonzalez
@ 2019-03-29 14:00   ` Marc Gonzalez
  0 siblings, 0 replies; 9+ messages in thread
From: Marc Gonzalez @ 2019-03-29 14:00 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Kishon Vijay Abraham I, MSM, LKML, Can Guo, Vivek Gautam,
	Evan Green, Jeffrey Hugo

On 22/03/2019 14:42, Marc Gonzalez wrote:

> On 26/02/2019 07:59, Bjorn Andersson wrote:
> 
>> @@ -1384,6 +1536,11 @@ static int qcom_qmp_phy_init(struct phy *phy)
>>  
>>  	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
>>  
>> +	if (cfg->pcs_misc_tbl) {
>> +		qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
>> +				       cfg->pcs_misc_tbl_num);
>> +	}
>> +
>>  	/*
>>  	 * UFS PHY requires the deassert of software reset before serdes start.
>>  	 * For UFS PHYs that do not have software reset control bits, defer
> 
> I think it would be better to configure pcs_misc *before* pcs.
> That would be closer to what downstream does (for 835 and 845 at least).
> 
> Also you don't need to test for NULL as that is already done in
> qcom_qmp_phy_configure() -- and in fact even that test is redundant,
> since the array is not dereferenced when count is 0.
> 
> When are you planning on sending a v2 of your PCIe series?

I split my comments across 3 messages. Have you seen them all?
(And taken them into account?)

Note: I folded the drivers/phy/qualcomm/phy-qcom-qmp.h definitions within
[PATCH v3 1/2] phy: qcom-qmp: Add msm8998 PCIe QMP PHY support

Regards.

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-03-29 14:00 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-26  6:59 [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Bjorn Andersson
2019-02-27  9:27 ` Marc Gonzalez
2019-02-27 18:09   ` Bjorn Andersson
2019-02-27 13:48 ` Marc Gonzalez
2019-03-22 13:42 ` Marc Gonzalez
2019-03-29 14:00   ` Marc Gonzalez
2019-03-22 15:34 ` Evan Green
2019-03-22 15:34   ` Evan Green
2019-03-26 14:59 ` Rob Herring

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