From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=quantatw.com (client-ip=219.87.191.90; helo=mx01.quantatw.com; envelope-from=prvs=983ed3b27=fran.hsu@quantatw.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=quantatw.com Received: from mx01.quantatw.com (mx01.quantatw.com [219.87.191.90]) by lists.ozlabs.org (Postfix) with ESMTP id 44VSqb42WNzDqGM for ; Fri, 29 Mar 2019 02:05:58 +1100 (AEDT) Received: from unknown (HELO mailbx06.quanta.corp) ([10.243.91.101]) by mx01.quantatw.com with ESMTP; 28 Mar 2019 23:05:56 +0800 Received: from localhost.localdomain (10.243.91.252) by mailbx06.quanta.corp (10.243.91.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 28 Mar 2019 23:05:55 +0800 From: To: Joel Stanley CC: , , , FranHsu Subject: [PATCH dev-5.0 v1 1/3] ARM: dts: nuvoton: Add Quanta GSJ BMC machine. Date: Thu, 28 Mar 2019 23:05:46 +0800 Message-ID: <20190328150548.3279-1-fran.hsu@quantatw.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.243.91.252] X-ClientProxiedBy: mailbx05.quanta.corp (10.243.91.100) To mailbx06.quanta.corp (10.243.91.101) X-TM-AS-Product-Ver: SMEX-12.0.0.1727-8.200.1013-24516.007 X-TM-AS-Result: No--4.290900-0.000000-31 X-TM-AS-MatchedID: 712203-704421-708712-701016-703529-704425-188019-700324-1 21336-702796-700264-702898-700019-847298-780012-148004-148036-10013-42000-4 2003-63 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Mar 2019 15:06:04 -0000 X-List-Received-Date: Thu, 28 Mar 2019 15:06:04 -0000 X-List-Received-Date: Thu, 28 Mar 2019 15:06:04 -0000 X-List-Received-Date: Thu, 28 Mar 2019 15:06:04 -0000 From: FranHsu Add a common device tree include file for NPCM730. Signed-off-by: FranHsu --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 57 ++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..20e13489b993 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; + + ahb { + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd0000 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + }; +}; -- 2.21.0