From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8049EC43381 for ; Fri, 29 Mar 2019 14:27:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4E6132173C for ; Fri, 29 Mar 2019 14:27:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alien8.de header.i=@alien8.de header.b="Ty8Kn1Ii" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729466AbfC2O1j (ORCPT ); Fri, 29 Mar 2019 10:27:39 -0400 Received: from mail.skyhub.de ([5.9.137.197]:46822 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729046AbfC2O1i (ORCPT ); Fri, 29 Mar 2019 10:27:38 -0400 Received: from zn.tnic (p200300EC2F148A000C2303278B6F16CD.dip0.t-ipconnect.de [IPv6:2003:ec:2f14:8a00:c23:327:8b6f:16cd]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 7A7941EC02C1; Fri, 29 Mar 2019 15:27:36 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1553869656; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=g66Y9KQ8P8D4SbrmnoAJ95U1RhuiyI40icRHIUKJjwA=; b=Ty8Kn1IiSdyJTwi6+WRedQVwaE0a/qMXyVVG9aQFGdFmc7DD+SYoh0cWFzptlZapdtHyQY Wb0Yt5LtQfJ3PraLnoCIVq1Qra4r+wsQdbpl+epgmPcTj/k+smSLZpKisXKkvlstymirkR rtJX4CvscEoJlKnt6ROcStXPWCrIHSM= Date: Fri, 29 Mar 2019 15:27:39 +0100 From: Borislav Petkov To: Rob Herring Cc: James Morse , Yash Shah , linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , "linux-kernel@vger.kernel.org" , Mark Rutland , Albert Ou , Mauro Carvalho Chehab , devicetree@vger.kernel.org Subject: Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Message-ID: <20190329142739.GG21152@zn.tnic> References: <1552382461-13051-1-git-send-email-yash.shah@sifive.com> <1552382461-13051-2-git-send-email-yash.shah@sifive.com> <20190328131657.GA9056@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 29, 2019 at 09:11:24AM -0500, Rob Herring wrote: > I honestly don't understand the issue with EDAC is here. The EDAC core supports only one driver and if you need to load more, you need to dance around that. Also, if those drivers need to talk amongst each other, then they need to build something ad-hoc so that they can. And the other architectures can very well do one driver per platform - only ARM wants to do this special thing because DT said so. Or whatever. > Highbank is separate drivers for L2 ECC (PL310) and DDR. Both are used > on highbank. That's because your L2 driver does allocate an edac_device (edac_device_alloc_ctl_info()) and the DDR one an edac_mc (edac_mc_add_mc_with_groups). For example, altera_edac does edac_device_alloc_ctl_info() for each IP block just fine. So a single driver *can* work. > Only the DDR driver is used midway. (I think we never got around to > how to report A15 L2 ECC errors within Linux.) > > In any case, it's all irrelevant to the DT binding. We don't design > bindings around what some particular OS wants. And just because DT dictates one driver per IP block, I'm not going to redesign EDAC to fit that scheme. You or someone else who feels strongly about it, is more than welcome to do so, of course. And then maintain it too. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller From: Borislav Petkov Message-Id: <20190329142739.GG21152@zn.tnic> Date: Fri, 29 Mar 2019 15:27:39 +0100 To: Rob Herring Cc: James Morse , Yash Shah , linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , "linux-kernel@vger.kernel.org" , Mark Rutland , Albert Ou , Mauro Carvalho Chehab , devicetree@vger.kernel.org List-ID: T24gRnJpLCBNYXIgMjksIDIwMTkgYXQgMDk6MTE6MjRBTSAtMDUwMCwgUm9iIEhlcnJpbmcgd3Jv dGU6Cj4gSSBob25lc3RseSBkb24ndCB1bmRlcnN0YW5kIHRoZSBpc3N1ZSB3aXRoIEVEQUMgaXMg aGVyZS4KClRoZSBFREFDIGNvcmUgc3VwcG9ydHMgb25seSBvbmUgZHJpdmVyIGFuZCBpZiB5b3Ug bmVlZCB0byBsb2FkIG1vcmUsIHlvdQpuZWVkIHRvIGRhbmNlIGFyb3VuZCB0aGF0LgoKQWxzbywg aWYgdGhvc2UgZHJpdmVycyBuZWVkIHRvIHRhbGsgYW1vbmdzdCBlYWNoIG90aGVyLCB0aGVuIHRo ZXkgbmVlZAp0byBidWlsZCBzb21ldGhpbmcgYWQtaG9jIHNvIHRoYXQgdGhleSBjYW4uCgpBbmQg dGhlIG90aGVyIGFyY2hpdGVjdHVyZXMgY2FuIHZlcnkgd2VsbCBkbyBvbmUgZHJpdmVyIHBlciBw bGF0Zm9ybSAtCm9ubHkgQVJNIHdhbnRzIHRvIGRvIHRoaXMgc3BlY2lhbCB0aGluZyBiZWNhdXNl IERUIHNhaWQgc28uIE9yIHdoYXRldmVyLgoKPiBIaWdoYmFuayBpcyBzZXBhcmF0ZSBkcml2ZXJz IGZvciBMMiBFQ0MgKFBMMzEwKSBhbmQgRERSLiBCb3RoIGFyZSB1c2VkCj4gb24gaGlnaGJhbmsu CgpUaGF0J3MgYmVjYXVzZSB5b3VyIEwyIGRyaXZlciBkb2VzIGFsbG9jYXRlIGFuIGVkYWNfZGV2 aWNlCihlZGFjX2RldmljZV9hbGxvY19jdGxfaW5mbygpKSBhbmQgdGhlIEREUiBvbmUgYW4gZWRh Y19tYwooZWRhY19tY19hZGRfbWNfd2l0aF9ncm91cHMpLgoKRm9yIGV4YW1wbGUsIGFsdGVyYV9l ZGFjIGRvZXMgZWRhY19kZXZpY2VfYWxsb2NfY3RsX2luZm8oKSBmb3IgZWFjaCBJUApibG9jayBq dXN0IGZpbmUuIFNvIGEgc2luZ2xlIGRyaXZlciAqY2FuKiB3b3JrLgoKPiBPbmx5IHRoZSBERFIg ZHJpdmVyIGlzIHVzZWQgbWlkd2F5LiAoSSB0aGluayB3ZSBuZXZlciBnb3QgYXJvdW5kIHRvCj4g aG93IHRvIHJlcG9ydCBBMTUgTDIgRUNDIGVycm9ycyB3aXRoaW4gTGludXguKQo+Cj4gSW4gYW55 IGNhc2UsIGl0J3MgYWxsIGlycmVsZXZhbnQgdG8gdGhlIERUIGJpbmRpbmcuIFdlIGRvbid0IGRl c2lnbgo+IGJpbmRpbmdzIGFyb3VuZCB3aGF0IHNvbWUgcGFydGljdWxhciBPUyB3YW50cy4KCkFu ZCBqdXN0IGJlY2F1c2UgRFQgZGljdGF0ZXMgb25lIGRyaXZlciBwZXIgSVAgYmxvY2ssIEknbSBu b3QgZ29pbmcgdG8KcmVkZXNpZ24gRURBQyB0byBmaXQgdGhhdCBzY2hlbWUuIFlvdSBvciBzb21l b25lIGVsc2Ugd2hvIGZlZWxzIHN0cm9uZ2x5CmFib3V0IGl0LCBpcyBtb3JlIHRoYW4gd2VsY29t ZSB0byBkbyBzbywgb2YgY291cnNlLiBBbmQgdGhlbiBtYWludGFpbiBpdAp0b28uCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D20F2C43381 for ; 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Fri, 29 Mar 2019 14:27:44 +0000 Received: from zn.tnic (p200300EC2F148A000C2303278B6F16CD.dip0.t-ipconnect.de [IPv6:2003:ec:2f14:8a00:c23:327:8b6f:16cd]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 7A7941EC02C1; Fri, 29 Mar 2019 15:27:36 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1553869656; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=g66Y9KQ8P8D4SbrmnoAJ95U1RhuiyI40icRHIUKJjwA=; b=Ty8Kn1IiSdyJTwi6+WRedQVwaE0a/qMXyVVG9aQFGdFmc7DD+SYoh0cWFzptlZapdtHyQY Wb0Yt5LtQfJ3PraLnoCIVq1Qra4r+wsQdbpl+epgmPcTj/k+smSLZpKisXKkvlstymirkR rtJX4CvscEoJlKnt6ROcStXPWCrIHSM= Date: Fri, 29 Mar 2019 15:27:39 +0100 From: Borislav Petkov To: Rob Herring Subject: Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Message-ID: <20190329142739.GG21152@zn.tnic> References: <1552382461-13051-1-git-send-email-yash.shah@sifive.com> <1552382461-13051-2-git-send-email-yash.shah@sifive.com> <20190328131657.GA9056@bogus> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190329_072742_753539_F4190C40 X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Albert Ou , Palmer Dabbelt , "linux-kernel@vger.kernel.org" , Yash Shah , James Morse , Paul Walmsley , linux-riscv@lists.infradead.org, Mauro Carvalho Chehab , linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Mar 29, 2019 at 09:11:24AM -0500, Rob Herring wrote: > I honestly don't understand the issue with EDAC is here. The EDAC core supports only one driver and if you need to load more, you need to dance around that. Also, if those drivers need to talk amongst each other, then they need to build something ad-hoc so that they can. And the other architectures can very well do one driver per platform - only ARM wants to do this special thing because DT said so. Or whatever. > Highbank is separate drivers for L2 ECC (PL310) and DDR. Both are used > on highbank. That's because your L2 driver does allocate an edac_device (edac_device_alloc_ctl_info()) and the DDR one an edac_mc (edac_mc_add_mc_with_groups). For example, altera_edac does edac_device_alloc_ctl_info() for each IP block just fine. So a single driver *can* work. > Only the DDR driver is used midway. (I think we never got around to > how to report A15 L2 ECC errors within Linux.) > > In any case, it's all irrelevant to the DT binding. We don't design > bindings around what some particular OS wants. And just because DT dictates one driver per IP block, I'm not going to redesign EDAC to fit that scheme. You or someone else who feels strongly about it, is more than welcome to do so, of course. And then maintain it too. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv