From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: Re: [PATCH v4 3/6] arm64: Handle trapped DC CVADP Date: Wed, 3 Apr 2019 14:21:31 +0100 Message-ID: <20190403132131.GR3567@e103592.cambridge.arm.com> References: <20190403105628.39798-1-andrew.murray@arm.com> <20190403105628.39798-4-andrew.murray@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Content-Disposition: inline In-Reply-To: <20190403105628.39798-4-andrew.murray@arm.com> To: Andrew Murray Cc: Catalin Marinas , Will Deacon , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, Mark Rutland , Phil Blundell , libc-alpha@sourceware.org, linux-api@vger.kernel.org, Suzuki K Poulose List-Id: linux-api@vger.kernel.org On Wed, Apr 03, 2019 at 11:56:25AM +0100, Andrew Murray wrote: > The ARMv8.5 DC CVADP instruction may be trapped to EL1 via > SCTLR_EL1.UCI therefore let's provide a handler for it. > > Just like the CVAP instruction we use a 'sys' instruction instead of > the 'dc' alias to avoid build issues with older toolchains. > > Signed-off-by: Andrew Murray > Reviewed-by: Mark Rutland Reviewed-by: Dave Martin > --- > arch/arm64/include/asm/esr.h | 3 ++- > arch/arm64/kernel/traps.c | 3 +++ > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index 52233f00d53d..07d5c026a0b3 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -198,9 +198,10 @@ > /* > * User space cache operations have the following sysreg encoding > * in System instructions. > - * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) > + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) > */ > #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 8ad119c3f665..f66e1ddbe4a7 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -459,6 +459,9 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) > case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ > __user_cache_maint("dc civac", address, ret); > break; > + case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ > + __user_cache_maint("sys 3, c7, c13, 1", address, ret); > + break; > case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ > __user_cache_maint("sys 3, c7, c12, 1", address, ret); > break; > -- > 2.21.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 357E7C4360F for ; Wed, 3 Apr 2019 13:21:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01BC62084C for ; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBfpr-0000nF-0r; Wed, 03 Apr 2019 13:21:47 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBfpg-0000ZH-BG for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2019 13:21:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B038A78; Wed, 3 Apr 2019 06:21:35 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CDFAC3F59C; Wed, 3 Apr 2019 06:21:33 -0700 (PDT) Date: Wed, 3 Apr 2019 14:21:31 +0100 From: Dave Martin To: Andrew Murray Subject: Re: [PATCH v4 3/6] arm64: Handle trapped DC CVADP Message-ID: <20190403132131.GR3567@e103592.cambridge.arm.com> References: <20190403105628.39798-1-andrew.murray@arm.com> <20190403105628.39798-4-andrew.murray@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190403105628.39798-4-andrew.murray@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190403_062136_759486_A514525E X-CRM114-Status: GOOD ( 19.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , libc-alpha@sourceware.org, Suzuki K Poulose , Szabolcs Nagy , Catalin Marinas , Will Deacon , Phil Blundell , linux-api@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 03, 2019 at 11:56:25AM +0100, Andrew Murray wrote: > The ARMv8.5 DC CVADP instruction may be trapped to EL1 via > SCTLR_EL1.UCI therefore let's provide a handler for it. > > Just like the CVAP instruction we use a 'sys' instruction instead of > the 'dc' alias to avoid build issues with older toolchains. > > Signed-off-by: Andrew Murray > Reviewed-by: Mark Rutland Reviewed-by: Dave Martin > --- > arch/arm64/include/asm/esr.h | 3 ++- > arch/arm64/kernel/traps.c | 3 +++ > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index 52233f00d53d..07d5c026a0b3 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -198,9 +198,10 @@ > /* > * User space cache operations have the following sysreg encoding > * in System instructions. > - * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) > + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) > */ > #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 > +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 > #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 8ad119c3f665..f66e1ddbe4a7 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -459,6 +459,9 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) > case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ > __user_cache_maint("dc civac", address, ret); > break; > + case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ > + __user_cache_maint("sys 3, c7, c13, 1", address, ret); > + break; > case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ > __user_cache_maint("sys 3, c7, c12, 1", address, ret); > break; > -- > 2.21.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel