From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D24A2C4360F for ; Thu, 4 Apr 2019 13:16:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A7261206C0 for ; Thu, 4 Apr 2019 13:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729052AbfDDNQ4 (ORCPT ); Thu, 4 Apr 2019 09:16:56 -0400 Received: from foss.arm.com ([217.140.101.70]:60118 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726790AbfDDNQ4 (ORCPT ); Thu, 4 Apr 2019 09:16:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84466A78; Thu, 4 Apr 2019 06:16:55 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9251E3F68F; Thu, 4 Apr 2019 06:16:53 -0700 (PDT) Date: Thu, 4 Apr 2019 14:16:42 +0100 From: Andre Przywara To: Zenghui Yu Cc: , , , , , , , , , Subject: Re: [PATCH] KVM: arm/arm64: vgic: Restrict setting irq->targets only in GICv2 Message-ID: <20190404141642.385daf5b@donnerap.cambridge.arm.com> In-Reply-To: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> References: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 4 Apr 2019 12:30:15 +0000 Zenghui Yu wrote: Hi, > Commit ad275b8bb1e6 ("KVM: arm/arm64: vgic-new: vgic_init: implement > vgic_init") had set irq->targets in kvm_vgic_vcpu_init(), regardless of > the GIC architecture (v2 or v3). When the number of vcpu reaches 32 > (in v3), UBSAN will complain about it. The first part looks similar to this one: http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/637209.html > ================================================================================ > UBSAN: Undefined behaviour in arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:223:21 > shift exponent 32 is too large for 32-bit type 'unsigned int' > CPU: 13 PID: 833 Comm: CPU 32/KVM Kdump: loaded Not tainted 5.1.0-rc1+ #16 > Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.58 10/24/2018 > Call trace: > dump_backtrace+0x0/0x190 > show_stack+0x24/0x30 > dump_stack+0xc8/0x114 > ubsan_epilogue+0x14/0x50 > __ubsan_handle_shift_out_of_bounds+0x118/0x188 > kvm_vgic_vcpu_init+0x1d4/0x200 > kvm_arch_vcpu_init+0x3c/0x48 > kvm_vcpu_init+0xa8/0x100 > kvm_arch_vcpu_create+0x94/0x120 > kvm_vm_ioctl+0x57c/0xe58 > do_vfs_ioctl+0xc4/0x7f0 > ksys_ioctl+0x8c/0xa0 > __arm64_sys_ioctl+0x28/0x38 > el0_svc_common+0xa0/0x190 > el0_svc_handler+0x38/0x78 > el0_svc+0x8/0xc > ================================================================================ > > This patch Restricts setting irq->targets in GICv2, which only supports > a maximum of eight PEs, to keep UBSAN quiet. And since irq->mpidr will > only be used by SPI in GICv3, we decided to set mpidr to 0 for SGI and > PPI. > > Like commit ab2d5eb03dbb ("KVM: arm/arm64: vgic: Always initialize the > group of private IRQs"), we should also take the creating order of the > VGIC and VCPUs into consideration. > > Cc: Eric Auger > Cc: Marc Zyngier > Cc: Andre Przywara > Cc: Christoffer Dall > Signed-off-by: Zenghui Yu > --- > virt/kvm/arm/vgic/vgic-init.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c > index 3bdb31e..0cba92e 100644 > --- a/virt/kvm/arm/vgic/vgic-init.c > +++ b/virt/kvm/arm/vgic/vgic-init.c > @@ -220,7 +220,6 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->intid = i; > irq->vcpu = NULL; > irq->target_vcpu = vcpu; > - irq->targets = 1U << vcpu->vcpu_id; > kref_init(&irq->refcount); > if (vgic_irq_is_sgi(i)) { > /* SGIs */ > @@ -231,10 +230,14 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->config = VGIC_CONFIG_LEVEL; > } > > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + if (vcpu->vcpu_id < VGIC_V2_MAX_CPUS) > + irq->targets = 1U << vcpu->vcpu_id; > + } > } > > if (!irqchip_in_kernel(vcpu->kvm)) > @@ -297,10 +300,13 @@ int vgic_init(struct kvm *kvm) > > for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) { > struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + irq->targets = 1U << vcpu->vcpu_id; > + } So why would you need this part? That does the same as above, doesn't it? Cheers, Andre. > } > } > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: Re: [PATCH] KVM: arm/arm64: vgic: Restrict setting irq->targets only in GICv2 Date: Thu, 4 Apr 2019 14:16:42 +0100 Message-ID: <20190404141642.385daf5b@donnerap.cambridge.arm.com> References: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: Zenghui Yu Cc: marc.zyngier@arm.com, christoffer.dall@arm.com, eric.auger@redhat.com, james.morse@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, wanghaibin.wang@huawei.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: kvmarm@lists.cs.columbia.edu On Thu, 4 Apr 2019 12:30:15 +0000 Zenghui Yu wrote: Hi, > Commit ad275b8bb1e6 ("KVM: arm/arm64: vgic-new: vgic_init: implement > vgic_init") had set irq->targets in kvm_vgic_vcpu_init(), regardless of > the GIC architecture (v2 or v3). When the number of vcpu reaches 32 > (in v3), UBSAN will complain about it. The first part looks similar to this one: http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/637209.html > ================================================================================ > UBSAN: Undefined behaviour in arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:223:21 > shift exponent 32 is too large for 32-bit type 'unsigned int' > CPU: 13 PID: 833 Comm: CPU 32/KVM Kdump: loaded Not tainted 5.1.0-rc1+ #16 > Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.58 10/24/2018 > Call trace: > dump_backtrace+0x0/0x190 > show_stack+0x24/0x30 > dump_stack+0xc8/0x114 > ubsan_epilogue+0x14/0x50 > __ubsan_handle_shift_out_of_bounds+0x118/0x188 > kvm_vgic_vcpu_init+0x1d4/0x200 > kvm_arch_vcpu_init+0x3c/0x48 > kvm_vcpu_init+0xa8/0x100 > kvm_arch_vcpu_create+0x94/0x120 > kvm_vm_ioctl+0x57c/0xe58 > do_vfs_ioctl+0xc4/0x7f0 > ksys_ioctl+0x8c/0xa0 > __arm64_sys_ioctl+0x28/0x38 > el0_svc_common+0xa0/0x190 > el0_svc_handler+0x38/0x78 > el0_svc+0x8/0xc > ================================================================================ > > This patch Restricts setting irq->targets in GICv2, which only supports > a maximum of eight PEs, to keep UBSAN quiet. And since irq->mpidr will > only be used by SPI in GICv3, we decided to set mpidr to 0 for SGI and > PPI. > > Like commit ab2d5eb03dbb ("KVM: arm/arm64: vgic: Always initialize the > group of private IRQs"), we should also take the creating order of the > VGIC and VCPUs into consideration. > > Cc: Eric Auger > Cc: Marc Zyngier > Cc: Andre Przywara > Cc: Christoffer Dall > Signed-off-by: Zenghui Yu > --- > virt/kvm/arm/vgic/vgic-init.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c > index 3bdb31e..0cba92e 100644 > --- a/virt/kvm/arm/vgic/vgic-init.c > +++ b/virt/kvm/arm/vgic/vgic-init.c > @@ -220,7 +220,6 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->intid = i; > irq->vcpu = NULL; > irq->target_vcpu = vcpu; > - irq->targets = 1U << vcpu->vcpu_id; > kref_init(&irq->refcount); > if (vgic_irq_is_sgi(i)) { > /* SGIs */ > @@ -231,10 +230,14 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->config = VGIC_CONFIG_LEVEL; > } > > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + if (vcpu->vcpu_id < VGIC_V2_MAX_CPUS) > + irq->targets = 1U << vcpu->vcpu_id; > + } > } > > if (!irqchip_in_kernel(vcpu->kvm)) > @@ -297,10 +300,13 @@ int vgic_init(struct kvm *kvm) > > for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) { > struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + irq->targets = 1U << vcpu->vcpu_id; > + } So why would you need this part? That does the same as above, doesn't it? Cheers, Andre. > } > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0EF9C4360F for ; Thu, 4 Apr 2019 13:17:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF08D206C0 for ; Thu, 4 Apr 2019 13:17:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EVHL7R/i" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF08D206C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0sVf9GvbTNhEasmjBajE9OFvF7sRK58k+jJAiyqYRn4=; b=EVHL7R/im5w/aS quJtTmeXrAFrT1B2d/C5Q/SHB+D63VNFJFezBCZPzfCyyCvJE6L9tyr6Z+waTff8AybOg4J6TVRgK 4aSMx+GQLsFlFk6WzWAtWG8Qu0oc/AluBVXpSe68QrWRSSvFRXe0MjZ4ZX+FWBeE1LmUb235TjY1h o88BXNRFeM6H35FbiNsDViim9sXPljYndbIzkRrIydmc51R1p+w6BeYzrvrWpjuo7Ar+fB4hrrWQ7 EseEaKoGlKInmhDxPGWhw4M70RmbXno1dTlqyS1S5HugXTzgK1+anIuVX/6dr7m8rk05T1zKSfbWg rqSgL/DBBRYopoJAkhSA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC2Ep-00033E-Qq; Thu, 04 Apr 2019 13:17:03 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC2Ej-00031c-Tu for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2019 13:17:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84466A78; Thu, 4 Apr 2019 06:16:55 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9251E3F68F; Thu, 4 Apr 2019 06:16:53 -0700 (PDT) Date: Thu, 4 Apr 2019 14:16:42 +0100 From: Andre Przywara To: Zenghui Yu Subject: Re: [PATCH] KVM: arm/arm64: vgic: Restrict setting irq->targets only in GICv2 Message-ID: <20190404141642.385daf5b@donnerap.cambridge.arm.com> In-Reply-To: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> References: <1554381015-13056-1-git-send-email-yuzenghui@huawei.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190404_061657_978201_25BEA345 X-CRM114-Status: GOOD ( 20.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, christoffer.dall@arm.com, linux-kernel@vger.kernel.org, eric.auger@redhat.com, james.morse@arm.com, wanghaibin.wang@huawei.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 4 Apr 2019 12:30:15 +0000 Zenghui Yu wrote: Hi, > Commit ad275b8bb1e6 ("KVM: arm/arm64: vgic-new: vgic_init: implement > vgic_init") had set irq->targets in kvm_vgic_vcpu_init(), regardless of > the GIC architecture (v2 or v3). When the number of vcpu reaches 32 > (in v3), UBSAN will complain about it. The first part looks similar to this one: http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/637209.html > ================================================================================ > UBSAN: Undefined behaviour in arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:223:21 > shift exponent 32 is too large for 32-bit type 'unsigned int' > CPU: 13 PID: 833 Comm: CPU 32/KVM Kdump: loaded Not tainted 5.1.0-rc1+ #16 > Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.58 10/24/2018 > Call trace: > dump_backtrace+0x0/0x190 > show_stack+0x24/0x30 > dump_stack+0xc8/0x114 > ubsan_epilogue+0x14/0x50 > __ubsan_handle_shift_out_of_bounds+0x118/0x188 > kvm_vgic_vcpu_init+0x1d4/0x200 > kvm_arch_vcpu_init+0x3c/0x48 > kvm_vcpu_init+0xa8/0x100 > kvm_arch_vcpu_create+0x94/0x120 > kvm_vm_ioctl+0x57c/0xe58 > do_vfs_ioctl+0xc4/0x7f0 > ksys_ioctl+0x8c/0xa0 > __arm64_sys_ioctl+0x28/0x38 > el0_svc_common+0xa0/0x190 > el0_svc_handler+0x38/0x78 > el0_svc+0x8/0xc > ================================================================================ > > This patch Restricts setting irq->targets in GICv2, which only supports > a maximum of eight PEs, to keep UBSAN quiet. And since irq->mpidr will > only be used by SPI in GICv3, we decided to set mpidr to 0 for SGI and > PPI. > > Like commit ab2d5eb03dbb ("KVM: arm/arm64: vgic: Always initialize the > group of private IRQs"), we should also take the creating order of the > VGIC and VCPUs into consideration. > > Cc: Eric Auger > Cc: Marc Zyngier > Cc: Andre Przywara > Cc: Christoffer Dall > Signed-off-by: Zenghui Yu > --- > virt/kvm/arm/vgic/vgic-init.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c > index 3bdb31e..0cba92e 100644 > --- a/virt/kvm/arm/vgic/vgic-init.c > +++ b/virt/kvm/arm/vgic/vgic-init.c > @@ -220,7 +220,6 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->intid = i; > irq->vcpu = NULL; > irq->target_vcpu = vcpu; > - irq->targets = 1U << vcpu->vcpu_id; > kref_init(&irq->refcount); > if (vgic_irq_is_sgi(i)) { > /* SGIs */ > @@ -231,10 +230,14 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) > irq->config = VGIC_CONFIG_LEVEL; > } > > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + if (vcpu->vcpu_id < VGIC_V2_MAX_CPUS) > + irq->targets = 1U << vcpu->vcpu_id; > + } > } > > if (!irqchip_in_kernel(vcpu->kvm)) > @@ -297,10 +300,13 @@ int vgic_init(struct kvm *kvm) > > for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) { > struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; > - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) > + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { > irq->group = 1; > - else > + irq->mpidr = 0; > + } else { > irq->group = 0; > + irq->targets = 1U << vcpu->vcpu_id; > + } So why would you need this part? That does the same as above, doesn't it? Cheers, Andre. > } > } > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel