From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Date: Thu, 4 Apr 2019 16:47:11 +0100 Message-ID: <20190404154711.GA27577@fuggles.cambridge.arm.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> Sender: linux-kernel-owner@vger.kernel.org To: Shameer Kolothum Cc: lorenzo.pieralisi@arm.com, robin.murphy@arm.com, andrew.murray@arm.com, jean-philippe.brucker@arm.com, mark.rutland@arm.com, guohanjun@huawei.com, john.garry@huawei.com, pabba@codeaurora.org, vkilari@codeaurora.org, rruigrok@codeaurora.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, neil.m.leeder@gmail.com List-Id: linux-acpi@vger.kernel.org On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > HiSilicon erratum 162001800 describes the limitation of > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > On these platforms, the PMCG event counter registers > (SMMU_PMCG_EVCNTRn) are read only and as a result it > is not possible to set the initial counter period value > on event monitor start. > > To work around this, the current value of the counter > is read and used for delta calculations. OEM information > from ACPI header is used to identify the affected hardware > platforms. > > Signed-off-by: Shameer Kolothum > Reviewed-by: Hanjun Guo > Reviewed-by: Robin Murphy > --- > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > drivers/perf/arm_smmuv3_pmu.c | 48 ++++++++++++++++++++++++++++++++++++------- > include/linux/acpi_iort.h | 1 + > 3 files changed, 57 insertions(+), 8 deletions(-) > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > index e2c9b26..4dc68de 100644 > --- a/drivers/acpi/arm64/iort.c > +++ b/drivers/acpi/arm64/iort.c > @@ -1366,9 +1366,23 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res, > ACPI_EDGE_SENSITIVE, &res[2]); > } > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > + /* HiSilicon Hip08 Platform */ > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, Passing integer constant 0 for the reason feels wrong to me. I'm going to change it to "Erratum #162001800" and also add an entry to silicon-errata.txt. Please shout if that's not ok. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20F1DC4360F for ; Thu, 4 Apr 2019 15:47:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0C65206BA for ; Thu, 4 Apr 2019 15:47:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OXfkQxN9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0C65206BA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IRzjNLqKd6w1GrgNldLgYcUSxabl+msaXsxesbKhGPU=; b=OXfkQxN9YDBh4v CqIefpQ8ykjQLy9fA8lMOtzDwDvcAw5zps2vCa8n19JpaYq+za2Q+l1kfrycG3JjFwTlZIEldPBRV IgmPGt8MlMrQXBHxbtAS65FkEPKmRndeHgteMu90qFjUMEMelkysJOxKMF7QmHuotn+COyvVnJDcB 0nbocZfA9Pmh7utFq1l7emV67W3yiic0Zgf4AeI5R46sU1XkoBRRcJ6ow0cAEXFpPBW89AmqevyyG rDP/UpfF4wuzdfDMskM40+pcrFjR+or+SZZvj30ozLts3nXWORpl2gHr8bU8iilxcCdFPceG8Q0L1 WjLBa2+/plAJNJ61EY0g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC4aI-0004fM-Pm; Thu, 04 Apr 2019 15:47:22 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC4aF-0004ew-O0 for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2019 15:47:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8569A169E; Thu, 4 Apr 2019 08:47:18 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D6FB43F59C; Thu, 4 Apr 2019 08:47:15 -0700 (PDT) Date: Thu, 4 Apr 2019 16:47:11 +0100 From: Will Deacon To: Shameer Kolothum Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Message-ID: <20190404154711.GA27577@fuggles.cambridge.arm.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190404_084719_787699_84FBFD7A X-CRM114-Status: GOOD ( 17.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, vkilari@codeaurora.org, lorenzo.pieralisi@arm.com, neil.m.leeder@gmail.com, jean-philippe.brucker@arm.com, pabba@codeaurora.org, john.garry@huawei.com, linuxarm@huawei.com, rruigrok@codeaurora.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, guohanjun@huawei.com, andrew.murray@arm.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > HiSilicon erratum 162001800 describes the limitation of > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > On these platforms, the PMCG event counter registers > (SMMU_PMCG_EVCNTRn) are read only and as a result it > is not possible to set the initial counter period value > on event monitor start. > > To work around this, the current value of the counter > is read and used for delta calculations. OEM information > from ACPI header is used to identify the affected hardware > platforms. > > Signed-off-by: Shameer Kolothum > Reviewed-by: Hanjun Guo > Reviewed-by: Robin Murphy > --- > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > drivers/perf/arm_smmuv3_pmu.c | 48 ++++++++++++++++++++++++++++++++++++------- > include/linux/acpi_iort.h | 1 + > 3 files changed, 57 insertions(+), 8 deletions(-) > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > index e2c9b26..4dc68de 100644 > --- a/drivers/acpi/arm64/iort.c > +++ b/drivers/acpi/arm64/iort.c > @@ -1366,9 +1366,23 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res, > ACPI_EDGE_SENSITIVE, &res[2]); > } > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > + /* HiSilicon Hip08 Platform */ > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, Passing integer constant 0 for the reason feels wrong to me. I'm going to change it to "Erratum #162001800" and also add an entry to silicon-errata.txt. Please shout if that's not ok. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel