From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: Re: [PATCH v7 19/27] KVM: arm64: Enumerate SVE register indices for KVM_GET_REG_LIST Date: Fri, 5 Apr 2019 10:35:45 +0100 Message-ID: <20190405093545.GK3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-20-git-send-email-Dave.Martin@arm.com> <20190404140832.5ryfi35df5skg4ke@kamzik.brq.redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6D8184A3A5 for ; Fri, 5 Apr 2019 05:35:52 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r00UqLuuYN5D for ; Fri, 5 Apr 2019 05:35:50 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by mm01.cs.columbia.edu (Postfix) with ESMTP id AFFD24A36D for ; Fri, 5 Apr 2019 05:35:50 -0400 (EDT) Content-Disposition: inline In-Reply-To: <20190404140832.5ryfi35df5skg4ke@kamzik.brq.redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Andrew Jones Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu On Thu, Apr 04, 2019 at 04:08:32PM +0200, Andrew Jones wrote: > On Fri, Mar 29, 2019 at 01:00:44PM +0000, Dave Martin wrote: > > This patch includes the SVE register IDs in the list returned by > > KVM_GET_REG_LIST, as appropriate. > > > > On a non-SVE-enabled vcpu, no new IDs are added. > > > > On an SVE-enabled vcpu, IDs for the FPSIMD V-registers are removed > > from the list, since userspace is required to access the Z- > > registers instead in order to access the V-register content. For > > the variably-sized SVE registers, the appropriate set of slice IDs > > are enumerated, depending on the maximum vector length for the > > vcpu. > > > > As it currently stands, the SVE architecture never requires more > > than one slice to exist per register, so this patch adds no > > explicit support for enumerating multiple slices. The code can be > > extended straightforwardly to support this in the future, if > > needed. > > > > Signed-off-by: Dave Martin > > Reviewed-by: Julien Thierry > > Tested-by: zhang.lei > > > > --- > > > > Changes since v6: > > > > * [Julien Thierry] Add a #define to replace the magic "slices = 1", > > and add a comment explaining to maintainers what needs to happen if > > this is updated in the future. > > > > Changes since v5: > > > > (Dropped Julien Thierry's Reviewed-by due to non-trivial rebasing) > > > > * Move mis-split reword to prevent put_user()s being accidentally the > > correct size from KVM: arm64/sve: Add pseudo-register for the guest's > > vector lengths. > > --- > > arch/arm64/kvm/guest.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 63 insertions(+) > > > > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > > index 736d8cb..2aa80a5 100644 > > --- a/arch/arm64/kvm/guest.c > > +++ b/arch/arm64/kvm/guest.c > > @@ -222,6 +222,13 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > > #define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0)) > > #define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0)) > > > > +/* > > + * number of register slices required to cover each whole SVE register on vcpu > > s/number/Number/ Not a sentence -> no capital letter. Due to the adjacent note it does look a little odd though. I'm happy to change it. > s/on vcpu// Agreed, I can drop that. > > + * NOTE: If you are tempted to modify this, you must also to rework > > s/to rework/rework/ Ack > > + * sve_reg_to_region() to match: > > + */ > > +#define vcpu_sve_slices(vcpu) 1 > > + > > /* Bounds of a single SVE register slice within vcpu->arch.sve_state */ > > struct sve_state_reg_region { > > unsigned int koffset; /* offset into sve_state in kernel memory */ > > @@ -411,6 +418,56 @@ static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > > return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; > > } > > > > +static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) > > +{ > > + /* Only the first slice ever exists, for now */ > > I'd move this comment up into the one above vcpu_sve_slices(), > and then nothing needs to change here when more slices come. > > > + const unsigned int slices = vcpu_sve_slices(vcpu); > > + > > + if (!vcpu_has_sve(vcpu)) > > + return 0; > > + > > + return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */); > > +} > > + > > +static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, > > + u64 __user *uindices) > > +{ > > + /* Only the first slice ever exists, for now */ > > Same comment as above. Fair point: this was to explain the magic "1" that was previously here, but the comments are a bit redundant here now: better to move the comments where the 1 itself went. > > + const unsigned int slices = vcpu_sve_slices(vcpu); > > + u64 reg; > > + unsigned int i, n; > > + int num_regs = 0; > > + > > + if (!vcpu_has_sve(vcpu)) > > + return 0; > > + > > + for (i = 0; i < slices; i++) { > > + for (n = 0; n < SVE_NUM_ZREGS; n++) { > > + reg = KVM_REG_ARM64_SVE_ZREG(n, i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > + > > + for (n = 0; n < SVE_NUM_PREGS; n++) { > > + reg = KVM_REG_ARM64_SVE_PREG(n, i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > + > > + reg = KVM_REG_ARM64_SVE_FFR(i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > nit: the extra blank lines above the num_regs++'s give the code an odd > look (to me) There's no guaranteed fall-through onto the increments: the blank line was there to highlight the fact that we may jump out using a return instead. But I'm happy enough to change it if you have a strong preference or you feel the code is equally clear without. > > > + > > + return num_regs; > > +} > > + > > /** > > * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG > > * > > @@ -421,6 +478,7 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) > > unsigned long res = 0; > > > > res += num_core_regs(vcpu); > > + res += num_sve_regs(vcpu); > > res += kvm_arm_num_sys_reg_descs(vcpu); > > res += kvm_arm_get_fw_num_regs(vcpu); > > res += NUM_TIMER_REGS; > > @@ -442,6 +500,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) > > return ret; > > uindices += ret; > > > > + ret = copy_sve_reg_indices(vcpu, uindices); > > + if (ret) > > + return ret; > > + uindices += ret; > > I know this if ret vs. if ret < 0 is being addressed already. Yes, Marc's patch in kvmarm/next should fix that. Cheers ---Dave From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BDEDC4360F for ; Fri, 5 Apr 2019 09:36:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E4CA217D4 for ; Fri, 5 Apr 2019 09:36:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hrGHjeiq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6E4CA217D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PQW5EMQilI7m9h7v13ax8W0lrA1+EtjpdNEGa5ciGz4=; b=hrGHjeiqED2O7A 3MlbbpNCj39bhr1XGipRn3VvfUCFMyVnmQnw/bUV7Za6+yA7CBQqbcDpT8cgC37P2PhCXWmnw6vEJ 7TzRURPdJlVVFLc5y6LqP9CHL8289yTeCiHPE6KywQIVMzBa7YyI7yDBsdtSGFnShhqr18NIsLxty kWh4WMqcN0MCpag1X2sALT3Sz0td3zrlqNWEPx8QMu3rl9fkjMAxOo8dlPBqL++R/gxo27cr9dQxM mkPjD0n9v47fa2z1/2IyKsXFhsxT9MFEDt4vLHSAxj7jHUdg0vGNloGJ+/1yN39kaJQwBnNtdGfmc Ng10Xu0FiAheE3m2nBrA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hCLGN-0002jU-21; Fri, 05 Apr 2019 09:35:55 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hCLGI-0002dy-MJ for linux-arm-kernel@lists.infradead.org; Fri, 05 Apr 2019 09:35:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 31406168F; Fri, 5 Apr 2019 02:35:50 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 405823F721; Fri, 5 Apr 2019 02:35:48 -0700 (PDT) Date: Fri, 5 Apr 2019 10:35:45 +0100 From: Dave Martin To: Andrew Jones Subject: Re: [PATCH v7 19/27] KVM: arm64: Enumerate SVE register indices for KVM_GET_REG_LIST Message-ID: <20190405093545.GK3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-20-git-send-email-Dave.Martin@arm.com> <20190404140832.5ryfi35df5skg4ke@kamzik.brq.redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190404140832.5ryfi35df5skg4ke@kamzik.brq.redhat.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190405_023551_314650_E32E83B5 X-CRM114-Status: GOOD ( 34.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 04, 2019 at 04:08:32PM +0200, Andrew Jones wrote: > On Fri, Mar 29, 2019 at 01:00:44PM +0000, Dave Martin wrote: > > This patch includes the SVE register IDs in the list returned by > > KVM_GET_REG_LIST, as appropriate. > > > > On a non-SVE-enabled vcpu, no new IDs are added. > > > > On an SVE-enabled vcpu, IDs for the FPSIMD V-registers are removed > > from the list, since userspace is required to access the Z- > > registers instead in order to access the V-register content. For > > the variably-sized SVE registers, the appropriate set of slice IDs > > are enumerated, depending on the maximum vector length for the > > vcpu. > > > > As it currently stands, the SVE architecture never requires more > > than one slice to exist per register, so this patch adds no > > explicit support for enumerating multiple slices. The code can be > > extended straightforwardly to support this in the future, if > > needed. > > > > Signed-off-by: Dave Martin > > Reviewed-by: Julien Thierry > > Tested-by: zhang.lei > > > > --- > > > > Changes since v6: > > > > * [Julien Thierry] Add a #define to replace the magic "slices = 1", > > and add a comment explaining to maintainers what needs to happen if > > this is updated in the future. > > > > Changes since v5: > > > > (Dropped Julien Thierry's Reviewed-by due to non-trivial rebasing) > > > > * Move mis-split reword to prevent put_user()s being accidentally the > > correct size from KVM: arm64/sve: Add pseudo-register for the guest's > > vector lengths. > > --- > > arch/arm64/kvm/guest.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 63 insertions(+) > > > > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > > index 736d8cb..2aa80a5 100644 > > --- a/arch/arm64/kvm/guest.c > > +++ b/arch/arm64/kvm/guest.c > > @@ -222,6 +222,13 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > > #define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0)) > > #define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0)) > > > > +/* > > + * number of register slices required to cover each whole SVE register on vcpu > > s/number/Number/ Not a sentence -> no capital letter. Due to the adjacent note it does look a little odd though. I'm happy to change it. > s/on vcpu// Agreed, I can drop that. > > + * NOTE: If you are tempted to modify this, you must also to rework > > s/to rework/rework/ Ack > > + * sve_reg_to_region() to match: > > + */ > > +#define vcpu_sve_slices(vcpu) 1 > > + > > /* Bounds of a single SVE register slice within vcpu->arch.sve_state */ > > struct sve_state_reg_region { > > unsigned int koffset; /* offset into sve_state in kernel memory */ > > @@ -411,6 +418,56 @@ static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > > return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; > > } > > > > +static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) > > +{ > > + /* Only the first slice ever exists, for now */ > > I'd move this comment up into the one above vcpu_sve_slices(), > and then nothing needs to change here when more slices come. > > > + const unsigned int slices = vcpu_sve_slices(vcpu); > > + > > + if (!vcpu_has_sve(vcpu)) > > + return 0; > > + > > + return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */); > > +} > > + > > +static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, > > + u64 __user *uindices) > > +{ > > + /* Only the first slice ever exists, for now */ > > Same comment as above. Fair point: this was to explain the magic "1" that was previously here, but the comments are a bit redundant here now: better to move the comments where the 1 itself went. > > + const unsigned int slices = vcpu_sve_slices(vcpu); > > + u64 reg; > > + unsigned int i, n; > > + int num_regs = 0; > > + > > + if (!vcpu_has_sve(vcpu)) > > + return 0; > > + > > + for (i = 0; i < slices; i++) { > > + for (n = 0; n < SVE_NUM_ZREGS; n++) { > > + reg = KVM_REG_ARM64_SVE_ZREG(n, i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > + > > + for (n = 0; n < SVE_NUM_PREGS; n++) { > > + reg = KVM_REG_ARM64_SVE_PREG(n, i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > + > > + reg = KVM_REG_ARM64_SVE_FFR(i); > > + if (put_user(reg, uindices++)) > > + return -EFAULT; > > + > > + num_regs++; > > + } > > nit: the extra blank lines above the num_regs++'s give the code an odd > look (to me) There's no guaranteed fall-through onto the increments: the blank line was there to highlight the fact that we may jump out using a return instead. But I'm happy enough to change it if you have a strong preference or you feel the code is equally clear without. > > > + > > + return num_regs; > > +} > > + > > /** > > * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG > > * > > @@ -421,6 +478,7 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) > > unsigned long res = 0; > > > > res += num_core_regs(vcpu); > > + res += num_sve_regs(vcpu); > > res += kvm_arm_num_sys_reg_descs(vcpu); > > res += kvm_arm_get_fw_num_regs(vcpu); > > res += NUM_TIMER_REGS; > > @@ -442,6 +500,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) > > return ret; > > uindices += ret; > > > > + ret = copy_sve_reg_indices(vcpu, uindices); > > + if (ret) > > + return ret; > > + uindices += ret; > > I know this if ret vs. if ret < 0 is being addressed already. Yes, Marc's patch in kvmarm/next should fix that. Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel