From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
intel-gvt-dev <intel-gvt-dev@lists.freedesktop.org>,
"Lv, Zhiyuan" <zhiyuan.lv@intel.com>,
"Yuan, Hang" <hang.yuan@intel.com>
Subject: [PULL] gvt-next
Date: Tue, 9 Apr 2019 12:05:00 +0800 [thread overview]
Message-ID: <20190409040500.GM17995@zhen-hp.sh.intel.com> (raw)
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Hi,
This includes various code refinement and cleanups, with proper
async/sync display flip handling, and also some changes required
for recent drm-intel-next as guest kernel, details below.
Thanks
--
The following changes since commit a01b2c6f47d86c7d1a9fa822b3b91ec233b61784:
drm/i915: Update DRIVER_DATE to 20190328 (2019-03-28 14:41:55 +0200)
are available in the Git repository at:
https://github.com/intel/gvt-linux.git tags/gvt-next-2019-04-09
for you to fetch changes up to 201e3e8580bb4924d0cc29fc3841ea5782401b46:
drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list (2019-04-03 16:37:20 +0800)
----------------------------------------------------------------
gvt-next-2019-04-09
- Refine range of MCHBAR snapshot (Yakui)
- Refine out-of-sync page struct (Yakui)
- Remove unused vGPU sreg (Yan)
- Refind MMIO reg names (Xiaolin)
- Proper handling of sync/async flip (Colin)
- Proper handling of PIPE_CONTROL/MI_FLUSH_DW index mode (Xiaolin)
- EXCC reg mask fix (Colin)
----------------------------------------------------------------
Colin Xu (5):
drm/i915/gvt: Use consist max display pipe numbers as i915 definition
drm/i915/gvt: Add macro define for mmio 0x50080 and gvt flip event
drm/i915/gvt: Enable synchronous flip on handling MI_DISPLAY_FLIP
drm/i915/gvt: Enable async flip on plane surface mmio writes
drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list
Xiaolin Zhang (2):
drm/i915/gvt: replaced register address with name
drm/i915/gvt: addressed guest GPU hang with HWS index mode
Yan Zhao (1):
drm/i915/gvt: remove the unused sreg
Zhao Yakui (2):
drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize gvt-g boot time
drm/i915/gvt: Refine the combined intel_vgpu_oos_page struct to save memory
Zhenyu Wang (1):
Merge tag 'drm-intel-next-2019-03-28' into gvt-next
drivers/gpu/drm/i915/gvt/cmd_parser.c | 30 +++++-
drivers/gpu/drm/i915/gvt/display.c | 1 -
drivers/gpu/drm/i915/gvt/gtt.c | 7 ++
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
drivers/gpu/drm/i915/gvt/gvt.h | 9 +-
drivers/gpu/drm/i915/gvt/handlers.c | 159 +++++++++++++++++++-------------
drivers/gpu/drm/i915/gvt/mmio.c | 8 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 4 +-
drivers/gpu/drm/i915/gvt/reg.h | 34 +++++++
9 files changed, 172 insertions(+), 82 deletions(-)
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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next reply other threads:[~2019-04-09 4:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-09 4:05 Zhenyu Wang [this message]
2019-04-16 7:29 ` [PULL] gvt-next Joonas Lahtinen
2019-04-16 8:48 ` Zhenyu Wang
2019-04-17 6:40 ` Joonas Lahtinen
-- strict thread matches above, loose matches on Subject: below --
2022-04-26 7:58 Wang, Zhi A
2022-04-26 7:58 ` Wang, Zhi A
2022-04-26 8:37 ` Jani Nikula
2022-04-26 8:37 ` Jani Nikula
2022-04-26 8:38 ` Wang, Zhi A
2022-04-26 8:38 ` Wang, Zhi A
2022-04-26 8:42 ` Wang, Zhi A
2022-04-26 8:42 ` Wang, Zhi A
2022-04-26 11:52 ` Jason Gunthorpe
2022-04-26 11:52 ` Jason Gunthorpe
2022-04-28 21:35 ` Alex Williamson
2022-04-28 21:35 ` Alex Williamson
2022-04-28 21:48 ` Alex Williamson
2022-04-28 21:48 ` Alex Williamson
2022-04-26 15:53 ` Jason Gunthorpe
2022-04-26 15:53 ` Jason Gunthorpe
2022-04-26 16:58 ` Wang, Zhi A
2022-04-26 16:58 ` Wang, Zhi A
2019-08-13 10:06 Zhenyu Wang
2019-08-13 20:48 ` Rodrigo Vivi
2019-02-01 6:15 Zhenyu Wang
2019-02-01 17:04 ` Rodrigo Vivi
2019-01-24 5:40 Zhenyu Wang
2019-01-31 18:02 ` Rodrigo Vivi
2018-06-19 9:00 Zhenyu Wang
2018-06-19 21:46 ` Rodrigo Vivi
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