On Fri, Apr 12, 2019 at 10:03:50PM -1000, Richard Henderson wrote:
> On 4/12/19 10:56 AM, Stafford Horne wrote:
> > I propose to incorporate the following into the openrisc spec.
> > 
> > Use proposals
> > 
> > P6 https://openrisc.io/proposals/lfmadd - clarification on internal rounding
> > (possibly exclude new madd instructions)
> > P7 https://openrisc.io/proposals/lstod-ldtos - convert between double and float
> > P9 https://openrisc.io/proposals/ladrp - New instruction for PIC code (already
> > in binutils)
> > P14 https://openrisc.io/proposals/orfpx64a32 - 64-bit fpu implemented in
> > marocchino (gcc/bintuils patches under review)
> > P11 https://openrisc.io/proposals/lfsf - add support for 'unordered' compares 
> > P13 https://openrisc.io/proposals/corrections - various corrections (possibly
> > exclude correction for l.ext* being mandatory as its not implemented everywhere)
> 
> As long as we're making changes, I propose to adjust ORFPX32 for OR64 such that
> the 32-bit result written back to the 64-bit register has the upper bits
> written as 0xffffffff.
> 
> For RISC-V this is called "NaN-boxing".  It means that if you attempt to use an
> f32 result as an f64 input you'll get an exception, since the input will be a
> Signaling NaN.

This makes sense.  I will add this in my updates as well.

> It's not complete, as we have not defined a 32-bit load that fills in
> 0xffffffff_00000000, but it'll get many incorrect uses.

We can add an instruction like `l.lwf` specifically for loading floats.

On 32-bit architectures it would be exactly the same as l.lwz, but on 64-bit it
can fill the upper bits with 0xffffffff.

Possible encoding:
   31    26    21    16     0
  [  0x1c  |  D  |  A  |  I  ]     l.lf

I can add it to the spec as a class II instruction.  We don't really need to
implement it until someone implements OR64.  But it will be good to have for
completeness as you pointed out.

Choosing the opcode as 0x1c as per below. (its close to l.lwa)

...
0x1a - unused
0x1b - l.lwa
0x1c - unused   <-- add l.lwf here
0x1d - l.cust2
0x1e - l.cust3
0x1f - l.cust4

(LOADs)
0x20 - l.ld
0x21 - l.lwz
0x22 - l.lws
0x23 - l.lbz
0x24 - l.lbs
0x25 - l.lhz
0x26 - l.lhs
(ALU IMM)
0x27 - l.addi
...

-Stafford