From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 718EAC282DA for ; Mon, 15 Apr 2019 15:17:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 37ED920818 for ; Mon, 15 Apr 2019 15:17:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=megous.com header.i=@megous.com header.b="ESu+LZ2E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727644AbfDOPRI (ORCPT ); Mon, 15 Apr 2019 11:17:08 -0400 Received: from vps.xff.cz ([195.181.215.36]:40262 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727252AbfDOPRH (ORCPT ); Mon, 15 Apr 2019 11:17:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1555341424; bh=8xwXVT3LW+zlhYrvlwYKn2Ag5zy2XOFiSQX1MCcT+mg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ESu+LZ2EEFWJEUmjvnv67TA4Iukv2ySu4cSoZ7rk9c1cvWuONCMhtWl+n3nzYKfy/ FC01GXLI7qMM+Xs40cK8QnsaqJiACtc4k+kQd6ORlqds9v/951vC7LF/JjwSOFuu3u VYNubqZ+LHm0Ack/xV8uVCzg8kLGyew46MyC28eA= Date: Mon, 15 Apr 2019 17:17:03 +0200 From: =?utf-8?Q?Ond=C5=99ej?= Jirman To: Chen-Yu Tsai Cc: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi Subject: Re: [linux-sunxi] [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC Message-ID: <20190415151703.svdosn3wbhk625jm@core.my.home> Mail-Followup-To: Chen-Yu Tsai , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 15, 2019 at 10:35:47PM +0800, Chen-Yu Tsai wrote: > On Mon, Apr 15, 2019 at 10:22 PM 'Ondřej Jirman' via linux-sunxi > wrote: > > > > Hi ChenYu, > > > > On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote: > > > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi > > > wrote: > > > > > > > > From: Ondrej Jirman > > > > > > > > I went through the datasheets for H6 and H5, and compared the differences. > > > > RTCs are largely similar, but not entirely compatible. Incompatibilities > > > > are in details not yet implemented by the rtc driver though. > > > > > > > > I also corrected the clock tree in H6 DTSI. > > > > > > Please also add DCXO clock input/output and XO clock input to the bindings > > > and DT, and also fix up the clock tree. You can skip them in the driver for > > > now, but please add a TODO. As long as you don't change the clock-output-name > > > of osc24M, everything should work as before. > > > > That's a bit confusing. There's no clock-output-name for osc24M, nor for input > > clock used in the dt-bindings or the driver. Perhaps you meant osc32k? Maybe > > I'm misunderstanding something? > > I meant the clock-output-names in the device node of the external 24M crystal. > > > If you look at the datasheet page 349, it looks like RTC provides "hosc" > > clock (to plls and the system) either from XO or DCXO oscillators. > > The default selection depends on the voltage level on external PAD. > > > > So based on what you wrote, I suggest these actual changes/names: > > > > 1) Add DT docs for HOSC clock provided at index 3: > > > > - 3: HOSC, 24MHz clock that clocks the PLLs and most of the SoC (H6 only) > > Correct. > > > 2) Add bindings description for "osc24M-dc", "osc24M-m" input clocks in > > addition to existing support for "osc32k". Name "osc24M-m" is based on > > X24MIN/MOUT pins and datasheet's "clk_24mxo" name. > > > > 3) The RTC driver would now just registers a fixed HOSC clock with a name > > gathered from the clock-output-names index 3 (if enabled by the new > > export_hosc flag - only enabled on H6). > > You don't need to do this part yet. Since the CCU drivers are hard-wired > (suprise) to use the global clock name "osc24M" as hosc source. The DT > references are only for show ATM, so it doesn't matter if you implement > the clocks in the RTC driver. Ah, so that's how it works. And that's what "clock parent rework" refers to! :) > However we want the DT to be correct, so that when we do get around to > doing it, we won't have to update the DT again. Ok, so I'll try to come up with a new set of patches, and we'll see if I'll get the description right. > It's up to you though. If you want to implement basic support, that's > fine by me. However you won't be able to test it without hacking the > CCU driver. > > After describing this, it seems that when we get to doing the clk parent > rework, we'll be in a bad situation if we don't get rtc changes in before > the CCU changes. Yeah. > > The driver would ignore the "osc24M-dc", "osc24M-m" input clocks. Or perhaps > > it could just support a case where only one of these are used and make it the > > only parent of the HOSC clock? > > They should just be DCXO and XO, based on the diagram. The names are local > to the RTC, so they don't need to be globally unique. Whatever matches the > datasheet is best. Ok. > > HOSC default source selection is done based on external PAD setup, and > > there's no need for runtime access/selection of HOSC source at the moment. > > Is it even possible to change it? Hmm. Looks like the answer is no: DCXO_CTRL_REG: - OSC_CLK_SRC_SEL bit: (Pad select) Read/Write column contains 'U' not (R/W) > > 4) In the future the RTC driver would be extended to support more refined > > setup/muxing/runtime selection of osc24M-dc/osc24M-m. PRCM driver would > > provide the osc24M-m clock, to be able for kernel to know how to gate it. > > > > The board's DTSI would have to link either "osc24M-dc", "osc24M-m" to nodes > > describing an external crystal (or to PRCM clock in the future). It's a boards > > choice on what crystals are actually used. 3 configs are possible - with one or > > two crystals, connected to either one of XIN/XOUT X24MIN/X24MOUT pins or both. > > AFAIK, osc24M-dc would link directly to the external crystal, while osc24M-m > would link to the external crystal first, then PRCM if it gets implemented. Ok. thank you, o. > > Would that work? > > > > DT would still probably need a re-work in the future, if the PRCM clock > > modeling the gate would be needed. > > Yeah. We'll deal with that when we get to it. > > > To summarize, the goal is to get the DT right the first time. > > Regards > ChenYu > > > > regards, > > o. > > > > > We just want the DT to describe what is actually there. For the XO input, > > > you could just directly reference the external crystal node. The gate for > > > it is likely somewhere in the PRCM block, which we don't have docs for. > > > > > > > There's a small detail here, that's not described absolutely correctly in > > > > DTSI, but the difference is not really that material. ext_osc32k is > > > > originally modelled as a fixed clock that feeds into RTC module, but in > > > > reality it's the RTC module that implements via its registers enabling and > > > > disabling of this oscillator/clock. > > > > > > > > Though: > > > > - there's no other possible user of ext_osc32k than RTC module > > > > - there's no other possible external configuration for the crystal > > > > circuit that would need to be handled in the dts per board > > > > > > > > So I guess, while the description is not perfect, this patch series still > > > > improves the current situation. Or maybe I'm misunderstanding something, > > > > and &ext_osc32k node just describes a fact that there's a crystal on > > > > the board. Then, everything is perhaps fine. :) > > > > > > Correct. The external clock nodes are modeling the crystal, not the internal > > > clock gate / distributor. > > > > > > Were the vendor to not include the crystal (for whatever reasons), the DT > > > should be able to describe it via the absence of the clock input, and the > > > driver should correctly use the internal (inaccurate) oscillator. I realize > > > the clocks property is required, and the driver doesn't handle this case > > > either, so we might have to fix that if it were to appear in the wild. > > > > > > > For now, the enable bit for this oscillator is toggled by the re-parenting > > > > code automatically, as needed. > > > > > > That's fine. No need to increase the clock tree depth. > > > > > > ChenYu > > > > > > > This patchset is necessary for implementing the WiFi/Bluetooth support > > > > on boards using H6 SoC. > > > > > > > > Please take a look. > > > > > > > > Thank you and regards, > > > > Ondrej Jirman > > > > > > > > Ondrej Jirman (3): > > > > dt-bindings: Add compatible for H6 RTC > > > > rtc: sun6i: Add support for H6 RTC > > > > arm64: dts: sun50i-h6: Add support for RTC and fix the clock tree > > > > > > > > .../devicetree/bindings/rtc/sun6i-rtc.txt | 1 + > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++------- > > > > drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++- > > > > 3 files changed, 55 insertions(+), 16 deletions(-) > > > > > > > > -- > > > > 2.21.0 > > > > > > > > -- > > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > > > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > > > > For more options, visit https://groups.google.com/d/optout. > > > > -- > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > > For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?=27Ond=C5=99ej_Jirman=27_via_linux=2Dsunxi?= Subject: Re: [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC Date: Mon, 15 Apr 2019 17:17:03 +0200 Message-ID: <20190415151703.svdosn3wbhk625jm@core.my.home> References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> Reply-To: megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi List-Id: devicetree@vger.kernel.org On Mon, Apr 15, 2019 at 10:35:47PM +0800, Chen-Yu Tsai wrote: > On Mon, Apr 15, 2019 at 10:22 PM 'Ond=C5=99ej Jirman' via linux-sunxi > wrote: > > > > Hi ChenYu, > > > > On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote: > > > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi > > > wrote: > > > > > > > > From: Ondrej Jirman > > > > > > > > I went through the datasheets for H6 and H5, and compared the diffe= rences. > > > > RTCs are largely similar, but not entirely compatible. Incompatibil= ities > > > > are in details not yet implemented by the rtc driver though. > > > > > > > > I also corrected the clock tree in H6 DTSI. > > > > > > Please also add DCXO clock input/output and XO clock input to the bin= dings > > > and DT, and also fix up the clock tree. You can skip them in the driv= er for > > > now, but please add a TODO. As long as you don't change the clock-out= put-name > > > of osc24M, everything should work as before. > > > > That's a bit confusing. There's no clock-output-name for osc24M, nor fo= r input > > clock used in the dt-bindings or the driver. Perhaps you meant osc32k? = Maybe > > I'm misunderstanding something? >=20 > I meant the clock-output-names in the device node of the external 24M cry= stal. >=20 > > If you look at the datasheet page 349, it looks like RTC provides "hosc= " > > clock (to plls and the system) either from XO or DCXO oscillators. > > The default selection depends on the voltage level on external PAD. > > > > So based on what you wrote, I suggest these actual changes/names: > > > > 1) Add DT docs for HOSC clock provided at index 3: > > > > - 3: HOSC, 24MHz clock that clocks the PLLs and most of the SoC (H6 o= nly) >=20 > Correct. >=20 > > 2) Add bindings description for "osc24M-dc", "osc24M-m" input clocks in > > addition to existing support for "osc32k". Name "osc24M-m" is based = on > > X24MIN/MOUT pins and datasheet's "clk_24mxo" name. > > > > 3) The RTC driver would now just registers a fixed HOSC clock with a na= me > > gathered from the clock-output-names index 3 (if enabled by the new > > export_hosc flag - only enabled on H6). >=20 > You don't need to do this part yet. Since the CCU drivers are hard-wired > (suprise) to use the global clock name "osc24M" as hosc source. The DT > references are only for show ATM, so it doesn't matter if you implement > the clocks in the RTC driver. Ah, so that's how it works. And that's what "clock parent rework" refers to! :) > However we want the DT to be correct, so that when we do get around to > doing it, we won't have to update the DT again. Ok, so I'll try to come up with a new set of patches, and we'll see if I'll get the description right. > It's up to you though. If you want to implement basic support, that's > fine by me. However you won't be able to test it without hacking the > CCU driver. >=20 > After describing this, it seems that when we get to doing the clk parent > rework, we'll be in a bad situation if we don't get rtc changes in before > the CCU changes. Yeah. > > The driver would ignore the "osc24M-dc", "osc24M-m" input clocks. Or= perhaps > > it could just support a case where only one of these are used and ma= ke it the > > only parent of the HOSC clock? >=20 > They should just be DCXO and XO, based on the diagram. The names are loca= l > to the RTC, so they don't need to be globally unique. Whatever matches th= e > datasheet is best. Ok. > > HOSC default source selection is done based on external PAD setup, a= nd > > there's no need for runtime access/selection of HOSC source at the m= oment. >=20 > Is it even possible to change it? Hmm. Looks like the answer is no: DCXO_CTRL_REG: - OSC_CLK_SRC_SEL bit: (Pad select) Read/Write column contains 'U' not (R/W) > > 4) In the future the RTC driver would be extended to support more refin= ed > > setup/muxing/runtime selection of osc24M-dc/osc24M-m. PRCM driver wo= uld > > provide the osc24M-m clock, to be able for kernel to know how to gat= e it. > > > > The board's DTSI would have to link either "osc24M-dc", "osc24M-m" to n= odes > > describing an external crystal (or to PRCM clock in the future). It's a= boards > > choice on what crystals are actually used. 3 configs are possible - wi= th one or > > two crystals, connected to either one of XIN/XOUT X24MIN/X24MOUT pins o= r both. >=20 > AFAIK, osc24M-dc would link directly to the external crystal, while osc24= M-m > would link to the external crystal first, then PRCM if it gets implemente= d. Ok. thank you, o. > > Would that work? > > > > DT would still probably need a re-work in the future, if the PRCM clock > > modeling the gate would be needed. >=20 > Yeah. We'll deal with that when we get to it. >=20 >=20 > To summarize, the goal is to get the DT right the first time. >=20 > Regards > ChenYu >=20 >=20 > > regards, > > o. > > > > > We just want the DT to describe what is actually there. For the XO in= put, > > > you could just directly reference the external crystal node. The gate= for > > > it is likely somewhere in the PRCM block, which we don't have docs fo= r. > > > > > > > There's a small detail here, that's not described absolutely correc= tly in > > > > DTSI, but the difference is not really that material. ext_osc32k is > > > > originally modelled as a fixed clock that feeds into RTC module, bu= t in > > > > reality it's the RTC module that implements via its registers enabl= ing and > > > > disabling of this oscillator/clock. > > > > > > > > Though: > > > > - there's no other possible user of ext_osc32k than RTC module > > > > - there's no other possible external configuration for the crystal > > > > circuit that would need to be handled in the dts per board > > > > > > > > So I guess, while the description is not perfect, this patch series= still > > > > improves the current situation. Or maybe I'm misunderstanding somet= hing, > > > > and &ext_osc32k node just describes a fact that there's a crystal o= n > > > > the board. Then, everything is perhaps fine. :) > > > > > > Correct. The external clock nodes are modeling the crystal, not the i= nternal > > > clock gate / distributor. > > > > > > Were the vendor to not include the crystal (for whatever reasons), th= e DT > > > should be able to describe it via the absence of the clock input, and= the > > > driver should correctly use the internal (inaccurate) oscillator. I r= ealize > > > the clocks property is required, and the driver doesn't handle this c= ase > > > either, so we might have to fix that if it were to appear in the wild= . > > > > > > > For now, the enable bit for this oscillator is toggled by the re-pa= renting > > > > code automatically, as needed. > > > > > > That's fine. No need to increase the clock tree depth. > > > > > > ChenYu > > > > > > > This patchset is necessary for implementing the WiFi/Bluetooth supp= ort > > > > on boards using H6 SoC. > > > > > > > > Please take a look. > > > > > > > > Thank you and regards, > > > > Ondrej Jirman > > > > > > > > Ondrej Jirman (3): > > > > dt-bindings: Add compatible for H6 RTC > > > > rtc: sun6i: Add support for H6 RTC > > > > arm64: dts: sun50i-h6: Add support for RTC and fix the clock tree > > > > > > > > .../devicetree/bindings/rtc/sun6i-rtc.txt | 1 + > > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++------- > > > > drivers/rtc/rtc-sun6i.c | 40 +++++++++++++++= +++- > > > > 3 files changed, 55 insertions(+), 16 deletions(-) > > > > > > > > -- > > > > 2.21.0 > > > > > > > > -- > > > > You received this message because you are subscribed to the Google = Groups "linux-sunxi" group. > > > > To unsubscribe from this group and stop receiving emails from it, s= end an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org > > > > For more options, visit https://groups.google.com/d/optout. > > > > -- > > You received this message because you are subscribed to the Google Grou= ps "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send = an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org > > For more options, visit https://groups.google.com/d/optout. --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. 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FC01GXLI7qMM+Xs40cK8QnsaqJiACtc4k+kQd6ORlqds9v/951vC7LF/JjwSOFuu3u VYNubqZ+LHm0Ack/xV8uVCzg8kLGyew46MyC28eA= Date: Mon, 15 Apr 2019 17:17:03 +0200 From: =?utf-8?Q?Ond=C5=99ej?= Jirman To: Chen-Yu Tsai Subject: Re: [linux-sunxi] [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC Message-ID: <20190415151703.svdosn3wbhk625jm@core.my.home> Mail-Followup-To: Chen-Yu Tsai , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_081706_208285_F2311BDA X-CRM114-Status: GOOD ( 51.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alessandro Zummo , Alexandre Belloni , devicetree , Maxime Ripard , linux-kernel , linux-sunxi , Rob Herring , linux-arm-kernel , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCBBcHIgMTUsIDIwMTkgYXQgMTA6MzU6NDdQTSArMDgwMCwgQ2hlbi1ZdSBUc2FpIHdy b3RlOgo+IE9uIE1vbiwgQXByIDE1LCAyMDE5IGF0IDEwOjIyIFBNICdPbmTFmWVqIEppcm1hbicg dmlhIGxpbnV4LXN1bnhpCj4gPGxpbnV4LXN1bnhpQGdvb2dsZWdyb3Vwcy5jb20+IHdyb3RlOgo+ ID4KPiA+IEhpIENoZW5ZdSwKPiA+Cj4gPiBPbiBNb24sIEFwciAxNSwgMjAxOSBhdCAwNDoxODox MlBNICswODAwLCBDaGVuLVl1IFRzYWkgd3JvdGU6Cj4gPiA+IE9uIEZyaSwgQXByIDEyLCAyMDE5 IGF0IDg6MDcgUE0gbWVnb3VzIHZpYSBsaW51eC1zdW54aQo+ID4gPiA8bGludXgtc3VueGlAZ29v Z2xlZ3JvdXBzLmNvbT4gd3JvdGU6Cj4gPiA+ID4KPiA+ID4gPiBGcm9tOiBPbmRyZWogSmlybWFu IDxtZWdvdXNAbWVnb3VzLmNvbT4KPiA+ID4gPgo+ID4gPiA+IEkgd2VudCB0aHJvdWdoIHRoZSBk YXRhc2hlZXRzIGZvciBINiBhbmQgSDUsIGFuZCBjb21wYXJlZCB0aGUgZGlmZmVyZW5jZXMuCj4g PiA+ID4gUlRDcyBhcmUgbGFyZ2VseSBzaW1pbGFyLCBidXQgbm90IGVudGlyZWx5IGNvbXBhdGli bGUuIEluY29tcGF0aWJpbGl0aWVzCj4gPiA+ID4gYXJlIGluIGRldGFpbHMgbm90IHlldCBpbXBs ZW1lbnRlZCBieSB0aGUgcnRjIGRyaXZlciB0aG91Z2guCj4gPiA+ID4KPiA+ID4gPiBJIGFsc28g Y29ycmVjdGVkIHRoZSBjbG9jayB0cmVlIGluIEg2IERUU0kuCj4gPiA+Cj4gPiA+IFBsZWFzZSBh bHNvIGFkZCBEQ1hPIGNsb2NrIGlucHV0L291dHB1dCBhbmQgWE8gY2xvY2sgaW5wdXQgdG8gdGhl IGJpbmRpbmdzCj4gPiA+IGFuZCBEVCwgYW5kIGFsc28gZml4IHVwIHRoZSBjbG9jayB0cmVlLiBZ b3UgY2FuIHNraXAgdGhlbSBpbiB0aGUgZHJpdmVyIGZvcgo+ID4gPiBub3csIGJ1dCBwbGVhc2Ug YWRkIGEgVE9ETy4gQXMgbG9uZyBhcyB5b3UgZG9uJ3QgY2hhbmdlIHRoZSBjbG9jay1vdXRwdXQt bmFtZQo+ID4gPiBvZiBvc2MyNE0sIGV2ZXJ5dGhpbmcgc2hvdWxkIHdvcmsgYXMgYmVmb3JlLgo+ ID4KPiA+IFRoYXQncyBhIGJpdCBjb25mdXNpbmcuIFRoZXJlJ3Mgbm8gY2xvY2stb3V0cHV0LW5h bWUgZm9yIG9zYzI0TSwgbm9yIGZvciBpbnB1dAo+ID4gY2xvY2sgdXNlZCBpbiB0aGUgZHQtYmlu ZGluZ3Mgb3IgdGhlIGRyaXZlci4gUGVyaGFwcyB5b3UgbWVhbnQgb3NjMzJrPyBNYXliZQo+ID4g SSdtIG1pc3VuZGVyc3RhbmRpbmcgc29tZXRoaW5nPwo+IAo+IEkgbWVhbnQgdGhlIGNsb2NrLW91 dHB1dC1uYW1lcyBpbiB0aGUgZGV2aWNlIG5vZGUgb2YgdGhlIGV4dGVybmFsIDI0TSBjcnlzdGFs Lgo+IAo+ID4gSWYgeW91IGxvb2sgYXQgdGhlIGRhdGFzaGVldCBwYWdlIDM0OSwgaXQgbG9va3Mg bGlrZSBSVEMgcHJvdmlkZXMgImhvc2MiCj4gPiBjbG9jayAodG8gcGxscyBhbmQgdGhlIHN5c3Rl bSkgZWl0aGVyIGZyb20gWE8gb3IgRENYTyBvc2NpbGxhdG9ycy4KPiA+IFRoZSBkZWZhdWx0IHNl bGVjdGlvbiBkZXBlbmRzIG9uIHRoZSB2b2x0YWdlIGxldmVsIG9uIGV4dGVybmFsIFBBRC4KPiA+ Cj4gPiBTbyBiYXNlZCBvbiB3aGF0IHlvdSB3cm90ZSwgSSBzdWdnZXN0IHRoZXNlIGFjdHVhbCBj aGFuZ2VzL25hbWVzOgo+ID4KPiA+IDEpIEFkZCBEVCBkb2NzIGZvciBIT1NDIGNsb2NrIHByb3Zp ZGVkIGF0IGluZGV4IDM6Cj4gPgo+ID4gICAtIDM6IEhPU0MsIDI0TUh6IGNsb2NrIHRoYXQgY2xv Y2tzIHRoZSBQTExzIGFuZCBtb3N0IG9mIHRoZSBTb0MgKEg2IG9ubHkpCj4gCj4gQ29ycmVjdC4K PiAKPiA+IDIpIEFkZCBiaW5kaW5ncyBkZXNjcmlwdGlvbiBmb3IgIm9zYzI0TS1kYyIsICJvc2My NE0tbSIgaW5wdXQgY2xvY2tzIGluCj4gPiAgICBhZGRpdGlvbiB0byBleGlzdGluZyBzdXBwb3J0 IGZvciAib3NjMzJrIi4gTmFtZSAib3NjMjRNLW0iIGlzIGJhc2VkIG9uCj4gPiAgICBYMjRNSU4v TU9VVCBwaW5zIGFuZCBkYXRhc2hlZXQncyAiY2xrXzI0bXhvIiBuYW1lLgo+ID4KPiA+IDMpIFRo ZSBSVEMgZHJpdmVyIHdvdWxkIG5vdyBqdXN0IHJlZ2lzdGVycyBhIGZpeGVkIEhPU0MgY2xvY2sg d2l0aCBhIG5hbWUKPiA+ICAgIGdhdGhlcmVkIGZyb20gdGhlIGNsb2NrLW91dHB1dC1uYW1lcyBp bmRleCAzIChpZiBlbmFibGVkIGJ5IHRoZSBuZXcKPiA+ICAgIGV4cG9ydF9ob3NjIGZsYWcgLSBv bmx5IGVuYWJsZWQgb24gSDYpLgo+IAo+IFlvdSBkb24ndCBuZWVkIHRvIGRvIHRoaXMgcGFydCB5 ZXQuIFNpbmNlIHRoZSBDQ1UgZHJpdmVycyBhcmUgaGFyZC13aXJlZAo+IChzdXByaXNlKSB0byB1 c2UgdGhlIGdsb2JhbCBjbG9jayBuYW1lICJvc2MyNE0iIGFzIGhvc2Mgc291cmNlLiBUaGUgRFQK PiByZWZlcmVuY2VzIGFyZSBvbmx5IGZvciBzaG93IEFUTSwgc28gaXQgZG9lc24ndCBtYXR0ZXIg aWYgeW91IGltcGxlbWVudAo+IHRoZSBjbG9ja3MgaW4gdGhlIFJUQyBkcml2ZXIuCgpBaCwgc28g dGhhdCdzIGhvdyBpdCB3b3Jrcy4gQW5kIHRoYXQncyB3aGF0ICJjbG9jayBwYXJlbnQgcmV3b3Jr IiByZWZlcnMKdG8hIDopCgo+IEhvd2V2ZXIgd2Ugd2FudCB0aGUgRFQgdG8gYmUgY29ycmVjdCwg c28gdGhhdCB3aGVuIHdlIGRvIGdldCBhcm91bmQgdG8KPiBkb2luZyBpdCwgd2Ugd29uJ3QgaGF2 ZSB0byB1cGRhdGUgdGhlIERUIGFnYWluLgoKT2ssIHNvIEknbGwgdHJ5IHRvIGNvbWUgdXAgd2l0 aCBhIG5ldyBzZXQgb2YgcGF0Y2hlcywgYW5kIHdlJ2xsIHNlZSBpZgpJJ2xsIGdldCB0aGUgZGVz Y3JpcHRpb24gcmlnaHQuCgo+IEl0J3MgdXAgdG8geW91IHRob3VnaC4gSWYgeW91IHdhbnQgdG8g aW1wbGVtZW50IGJhc2ljIHN1cHBvcnQsIHRoYXQncwo+IGZpbmUgYnkgbWUuIEhvd2V2ZXIgeW91 IHdvbid0IGJlIGFibGUgdG8gdGVzdCBpdCB3aXRob3V0IGhhY2tpbmcgdGhlCj4gQ0NVIGRyaXZl ci4KPiAKPiBBZnRlciBkZXNjcmliaW5nIHRoaXMsIGl0IHNlZW1zIHRoYXQgd2hlbiB3ZSBnZXQg dG8gZG9pbmcgdGhlIGNsayBwYXJlbnQKPiByZXdvcmssIHdlJ2xsIGJlIGluIGEgYmFkIHNpdHVh dGlvbiBpZiB3ZSBkb24ndCBnZXQgcnRjIGNoYW5nZXMgaW4gYmVmb3JlCj4gdGhlIENDVSBjaGFu Z2VzLgoKWWVhaC4KCj4gPiAgICBUaGUgZHJpdmVyIHdvdWxkIGlnbm9yZSB0aGUgIm9zYzI0TS1k YyIsICJvc2MyNE0tbSIgaW5wdXQgY2xvY2tzLiBPciBwZXJoYXBzCj4gPiAgICBpdCBjb3VsZCBq dXN0IHN1cHBvcnQgYSBjYXNlIHdoZXJlIG9ubHkgb25lIG9mIHRoZXNlIGFyZSB1c2VkIGFuZCBt YWtlIGl0IHRoZQo+ID4gICAgb25seSBwYXJlbnQgb2YgdGhlIEhPU0MgY2xvY2s/Cj4gCj4gVGhl eSBzaG91bGQganVzdCBiZSBEQ1hPIGFuZCBYTywgYmFzZWQgb24gdGhlIGRpYWdyYW0uIFRoZSBu YW1lcyBhcmUgbG9jYWwKPiB0byB0aGUgUlRDLCBzbyB0aGV5IGRvbid0IG5lZWQgdG8gYmUgZ2xv YmFsbHkgdW5pcXVlLiBXaGF0ZXZlciBtYXRjaGVzIHRoZQo+IGRhdGFzaGVldCBpcyBiZXN0LgoK T2suCgo+ID4gICAgSE9TQyBkZWZhdWx0IHNvdXJjZSBzZWxlY3Rpb24gaXMgZG9uZSBiYXNlZCBv biBleHRlcm5hbCBQQUQgc2V0dXAsIGFuZAo+ID4gICAgdGhlcmUncyBubyBuZWVkIGZvciBydW50 aW1lIGFjY2Vzcy9zZWxlY3Rpb24gb2YgSE9TQyBzb3VyY2UgYXQgdGhlIG1vbWVudC4KPiAKPiBJ cyBpdCBldmVuIHBvc3NpYmxlIHRvIGNoYW5nZSBpdD8KCkhtbS4gTG9va3MgbGlrZSB0aGUgYW5z d2VyIGlzIG5vOgoKRENYT19DVFJMX1JFRzoKICAtIE9TQ19DTEtfU1JDX1NFTCBiaXQ6CiAgICAo UGFkIHNlbGVjdCkKICAgIFJlYWQvV3JpdGUgY29sdW1uIGNvbnRhaW5zICdVJyBub3QgKFIvVykK Cj4gPiA0KSBJbiB0aGUgZnV0dXJlIHRoZSBSVEMgZHJpdmVyIHdvdWxkIGJlIGV4dGVuZGVkIHRv IHN1cHBvcnQgbW9yZSByZWZpbmVkCj4gPiAgICBzZXR1cC9tdXhpbmcvcnVudGltZSBzZWxlY3Rp b24gb2Ygb3NjMjRNLWRjL29zYzI0TS1tLiBQUkNNIGRyaXZlciB3b3VsZAo+ID4gICAgcHJvdmlk ZSB0aGUgb3NjMjRNLW0gY2xvY2ssIHRvIGJlIGFibGUgZm9yIGtlcm5lbCB0byBrbm93IGhvdyB0 byBnYXRlIGl0Lgo+ID4KPiA+IFRoZSBib2FyZCdzIERUU0kgd291bGQgaGF2ZSB0byBsaW5rIGVp dGhlciAib3NjMjRNLWRjIiwgIm9zYzI0TS1tIiB0byBub2Rlcwo+ID4gZGVzY3JpYmluZyBhbiBl eHRlcm5hbCBjcnlzdGFsIChvciB0byBQUkNNIGNsb2NrIGluIHRoZSBmdXR1cmUpLiBJdCdzIGEg Ym9hcmRzCj4gPiBjaG9pY2UgIG9uIHdoYXQgY3J5c3RhbHMgYXJlIGFjdHVhbGx5IHVzZWQuIDMg Y29uZmlncyBhcmUgcG9zc2libGUgLSB3aXRoIG9uZSBvcgo+ID4gdHdvIGNyeXN0YWxzLCBjb25u ZWN0ZWQgdG8gZWl0aGVyIG9uZSBvZiBYSU4vWE9VVCBYMjRNSU4vWDI0TU9VVCBwaW5zIG9yIGJv dGguCj4gCj4gQUZBSUssIG9zYzI0TS1kYyB3b3VsZCBsaW5rIGRpcmVjdGx5IHRvIHRoZSBleHRl cm5hbCBjcnlzdGFsLCB3aGlsZSBvc2MyNE0tbQo+IHdvdWxkIGxpbmsgdG8gdGhlIGV4dGVybmFs IGNyeXN0YWwgZmlyc3QsIHRoZW4gUFJDTSBpZiBpdCBnZXRzIGltcGxlbWVudGVkLgoKT2suCgp0 aGFuayB5b3UsCglvLgoKPiA+IFdvdWxkIHRoYXQgd29yaz8KPiA+Cj4gPiBEVCB3b3VsZCBzdGls bCBwcm9iYWJseSBuZWVkIGEgcmUtd29yayBpbiB0aGUgZnV0dXJlLCBpZiB0aGUgUFJDTSBjbG9j awo+ID4gbW9kZWxpbmcgdGhlIGdhdGUgd291bGQgYmUgbmVlZGVkLgo+IAo+IFllYWguIFdlJ2xs IGRlYWwgd2l0aCB0aGF0IHdoZW4gd2UgZ2V0IHRvIGl0Lgo+IAo+IAo+IFRvIHN1bW1hcml6ZSwg dGhlIGdvYWwgaXMgdG8gZ2V0IHRoZSBEVCByaWdodCB0aGUgZmlyc3QgdGltZS4KPiAKPiBSZWdh cmRzCj4gQ2hlbll1Cj4gCj4gCj4gPiByZWdhcmRzLAo+ID4gICBvLgo+ID4KPiA+ID4gV2UganVz dCB3YW50IHRoZSBEVCB0byBkZXNjcmliZSB3aGF0IGlzIGFjdHVhbGx5IHRoZXJlLiBGb3IgdGhl IFhPIGlucHV0LAo+ID4gPiB5b3UgY291bGQganVzdCBkaXJlY3RseSByZWZlcmVuY2UgdGhlIGV4 dGVybmFsIGNyeXN0YWwgbm9kZS4gVGhlIGdhdGUgZm9yCj4gPiA+IGl0IGlzIGxpa2VseSBzb21l d2hlcmUgaW4gdGhlIFBSQ00gYmxvY2ssIHdoaWNoIHdlIGRvbid0IGhhdmUgZG9jcyBmb3IuCj4g PiA+Cj4gPiA+ID4gVGhlcmUncyBhIHNtYWxsIGRldGFpbCBoZXJlLCB0aGF0J3Mgbm90IGRlc2Ny aWJlZCBhYnNvbHV0ZWx5IGNvcnJlY3RseSBpbgo+ID4gPiA+IERUU0ksIGJ1dCB0aGUgZGlmZmVy ZW5jZSBpcyBub3QgcmVhbGx5IHRoYXQgbWF0ZXJpYWwuIGV4dF9vc2MzMmsgaXMKPiA+ID4gPiBv cmlnaW5hbGx5IG1vZGVsbGVkIGFzIGEgZml4ZWQgY2xvY2sgdGhhdCBmZWVkcyBpbnRvIFJUQyBt b2R1bGUsIGJ1dCBpbgo+ID4gPiA+IHJlYWxpdHkgaXQncyB0aGUgUlRDIG1vZHVsZSB0aGF0IGlt cGxlbWVudHMgdmlhIGl0cyByZWdpc3RlcnMgZW5hYmxpbmcgYW5kCj4gPiA+ID4gZGlzYWJsaW5n IG9mIHRoaXMgb3NjaWxsYXRvci9jbG9jay4KPiA+ID4gPgo+ID4gPiA+IFRob3VnaDoKPiA+ID4g PiAtIHRoZXJlJ3Mgbm8gb3RoZXIgcG9zc2libGUgdXNlciBvZiBleHRfb3NjMzJrIHRoYW4gUlRD IG1vZHVsZQo+ID4gPiA+IC0gdGhlcmUncyBubyBvdGhlciBwb3NzaWJsZSBleHRlcm5hbCBjb25m aWd1cmF0aW9uIGZvciB0aGUgY3J5c3RhbAo+ID4gPiA+ICAgY2lyY3VpdCB0aGF0IHdvdWxkIG5l ZWQgdG8gYmUgaGFuZGxlZCBpbiB0aGUgZHRzIHBlciBib2FyZAo+ID4gPiA+Cj4gPiA+ID4gU28g SSBndWVzcywgd2hpbGUgdGhlIGRlc2NyaXB0aW9uIGlzIG5vdCBwZXJmZWN0LCB0aGlzIHBhdGNo IHNlcmllcyBzdGlsbAo+ID4gPiA+IGltcHJvdmVzIHRoZSBjdXJyZW50IHNpdHVhdGlvbi4gT3Ig bWF5YmUgSSdtIG1pc3VuZGVyc3RhbmRpbmcgc29tZXRoaW5nLAo+ID4gPiA+IGFuZCAmZXh0X29z YzMyayBub2RlIGp1c3QgZGVzY3JpYmVzIGEgZmFjdCB0aGF0IHRoZXJlJ3MgYSBjcnlzdGFsIG9u Cj4gPiA+ID4gdGhlIGJvYXJkLiBUaGVuLCBldmVyeXRoaW5nIGlzIHBlcmhhcHMgZmluZS4gOikK PiA+ID4KPiA+ID4gQ29ycmVjdC4gVGhlIGV4dGVybmFsIGNsb2NrIG5vZGVzIGFyZSBtb2RlbGlu ZyB0aGUgY3J5c3RhbCwgbm90IHRoZSBpbnRlcm5hbAo+ID4gPiBjbG9jayBnYXRlIC8gZGlzdHJp YnV0b3IuCj4gPiA+Cj4gPiA+IFdlcmUgdGhlIHZlbmRvciB0byBub3QgaW5jbHVkZSB0aGUgY3J5 c3RhbCAoZm9yIHdoYXRldmVyIHJlYXNvbnMpLCB0aGUgRFQKPiA+ID4gc2hvdWxkIGJlIGFibGUg dG8gZGVzY3JpYmUgaXQgdmlhIHRoZSBhYnNlbmNlIG9mIHRoZSBjbG9jayBpbnB1dCwgYW5kIHRo ZQo+ID4gPiBkcml2ZXIgc2hvdWxkIGNvcnJlY3RseSB1c2UgdGhlIGludGVybmFsIChpbmFjY3Vy YXRlKSBvc2NpbGxhdG9yLiBJIHJlYWxpemUKPiA+ID4gdGhlIGNsb2NrcyBwcm9wZXJ0eSBpcyBy ZXF1aXJlZCwgYW5kIHRoZSBkcml2ZXIgZG9lc24ndCBoYW5kbGUgdGhpcyBjYXNlCj4gPiA+IGVp dGhlciwgc28gd2UgbWlnaHQgaGF2ZSB0byBmaXggdGhhdCBpZiBpdCB3ZXJlIHRvIGFwcGVhciBp biB0aGUgd2lsZC4KPiA+ID4KPiA+ID4gPiBGb3Igbm93LCB0aGUgZW5hYmxlIGJpdCBmb3IgdGhp cyBvc2NpbGxhdG9yIGlzIHRvZ2dsZWQgYnkgdGhlIHJlLXBhcmVudGluZwo+ID4gPiA+IGNvZGUg YXV0b21hdGljYWxseSwgYXMgbmVlZGVkLgo+ID4gPgo+ID4gPiBUaGF0J3MgZmluZS4gTm8gbmVl ZCB0byBpbmNyZWFzZSB0aGUgY2xvY2sgdHJlZSBkZXB0aC4KPiA+ID4KPiA+ID4gQ2hlbll1Cj4g PiA+Cj4gPiA+ID4gVGhpcyBwYXRjaHNldCBpcyBuZWNlc3NhcnkgZm9yIGltcGxlbWVudGluZyB0 aGUgV2lGaS9CbHVldG9vdGggc3VwcG9ydAo+ID4gPiA+IG9uIGJvYXJkcyB1c2luZyBINiBTb0Mu Cj4gPiA+ID4KPiA+ID4gPiBQbGVhc2UgdGFrZSBhIGxvb2suCj4gPiA+ID4KPiA+ID4gPiBUaGFu ayB5b3UgYW5kIHJlZ2FyZHMsCj4gPiA+ID4gICBPbmRyZWogSmlybWFuCj4gPiA+ID4KPiA+ID4g PiBPbmRyZWogSmlybWFuICgzKToKPiA+ID4gPiAgIGR0LWJpbmRpbmdzOiBBZGQgY29tcGF0aWJs ZSBmb3IgSDYgUlRDCj4gPiA+ID4gICBydGM6IHN1bjZpOiBBZGQgc3VwcG9ydCBmb3IgSDYgUlRD Cj4gPiA+ID4gICBhcm02NDogZHRzOiBzdW41MGktaDY6IEFkZCBzdXBwb3J0IGZvciBSVEMgYW5k IGZpeCB0aGUgY2xvY2sgdHJlZQo+ID4gPiA+Cj4gPiA+ID4gIC4uLi9kZXZpY2V0cmVlL2JpbmRp bmdzL3J0Yy9zdW42aS1ydGMudHh0ICAgICB8ICAxICsKPiA+ID4gPiAgYXJjaC9hcm02NC9ib290 L2R0cy9hbGx3aW5uZXIvc3VuNTBpLWg2LmR0c2kgIHwgMzAgKysrKysrKy0tLS0tLS0KPiA+ID4g PiAgZHJpdmVycy9ydGMvcnRjLXN1bjZpLmMgICAgICAgICAgICAgICAgICAgICAgIHwgNDAgKysr KysrKysrKysrKysrKysrLQo+ID4gPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDU1IGluc2VydGlvbnMo KyksIDE2IGRlbGV0aW9ucygtKQo+ID4gPiA+Cj4gPiA+ID4gLS0KPiA+ID4gPiAyLjIxLjAKPiA+ ID4gPgo+ID4gPiA+IC0tCj4gPiA+ID4gWW91IHJlY2VpdmVkIHRoaXMgbWVzc2FnZSBiZWNhdXNl IHlvdSBhcmUgc3Vic2NyaWJlZCB0byB0aGUgR29vZ2xlIEdyb3VwcyAibGludXgtc3VueGkiIGdy b3VwLgo+ID4gPiA+IFRvIHVuc3Vic2NyaWJlIGZyb20gdGhpcyBncm91cCBhbmQgc3RvcCByZWNl aXZpbmcgZW1haWxzIGZyb20gaXQsIHNlbmQgYW4gZW1haWwgdG8gbGludXgtc3VueGkrdW5zdWJz Y3JpYmVAZ29vZ2xlZ3JvdXBzLmNvbS4KPiA+ID4gPiBGb3IgbW9yZSBvcHRpb25zLCB2aXNpdCBo dHRwczovL2dyb3Vwcy5nb29nbGUuY29tL2Qvb3B0b3V0Lgo+ID4KPiA+IC0tCj4gPiBZb3UgcmVj ZWl2ZWQgdGhpcyBtZXNzYWdlIGJlY2F1c2UgeW91IGFyZSBzdWJzY3JpYmVkIHRvIHRoZSBHb29n bGUgR3JvdXBzICJsaW51eC1zdW54aSIgZ3JvdXAuCj4gPiBUbyB1bnN1YnNjcmliZSBmcm9tIHRo aXMgZ3JvdXAgYW5kIHN0b3AgcmVjZWl2aW5nIGVtYWlscyBmcm9tIGl0LCBzZW5kIGFuIGVtYWls IHRvIGxpbnV4LXN1bnhpK3Vuc3Vic2NyaWJlQGdvb2dsZWdyb3Vwcy5jb20uCj4gPiBGb3IgbW9y ZSBvcHRpb25zLCB2aXNpdCBodHRwczovL2dyb3Vwcy5nb29nbGUuY29tL2Qvb3B0b3V0LgoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtl cm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5l bAo=