From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:40759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGYnT-0007tm-Qs for qemu-devel@nongnu.org; Tue, 16 Apr 2019 20:51:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGYnS-0000M9-Qb for qemu-devel@nongnu.org; Tue, 16 Apr 2019 20:51:31 -0400 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:37057) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGYnS-0000Lg-EW for qemu-devel@nongnu.org; Tue, 16 Apr 2019 20:51:30 -0400 Received: by mail-io1-xd44.google.com with SMTP id x7so19221169ioh.4 for ; Tue, 16 Apr 2019 17:51:29 -0700 (PDT) From: Stephen Checkoway Date: Tue, 16 Apr 2019 20:50:53 -0400 Message-Id: <20190417005053.885-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2] hw/char/escc: Lower irq when transmit buffer is filled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Stephen Checkoway , QEMU Developers , Artyom Tarasenko , Laurent Vivier , qemu-trivial@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Mark Cave-Ayland The SCC/ESCC will briefly stop asserting an interrupt when the transmit FIFO is filled. This code doesn't model the transmit FIFO/shift register so the pending transmit interrupt is never deasserted which means that an edge-triggered interrupt controller will never see the low-to-high transition it needs to raise another interrupt. The practical consequence of this is that guest firmware with an interrupt service routine for the ESCC that does not send all of the data it has immediately will stop sending data if the following sequence of events occurs: 1. Disable processor interrupts 2. Write a character to the ESCC 3. Add additional characters to a buffer which is drained by the ISR 4. Enable processor interrupts In this case, the first character will be sent, the interrupt will fire and the ISR will output the second character. Since the pending transmit interrupt remains asserted, no additional interrupts will ever fire. This fixes that situation by explicitly lowering the IRQ when a character is written to the buffer and no other interrupts are currently pending. Signed-off-by: Stephen Checkoway --- hw/char/escc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/char/escc.c b/hw/char/escc.c index 628f5f81f7..c5b05a63f1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -509,6 +509,13 @@ static void escc_mem_write(void *opaque, hwaddr addr, break; case SERIAL_DATA: trace_escc_mem_writeb_data(CHN_C(s), val); + /* + * Lower the irq when data is written to the Tx buffer and no other + * interrupts are currently pending. The irq will be raised again once + * the Tx buffer becomes empty below. + */ + s->txint = 0; + escc_update_irq(s); s->tx = val; if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled if (qemu_chr_fe_backend_connected(&s->chr)) { -- 2.20.1 (Apple Git-117)