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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 19 Apr 2019 18:54:49 +0100 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x3JHsnW734996446 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 19 Apr 2019 17:54:49 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EDBCCB2067; Fri, 19 Apr 2019 17:54:48 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D00D3B2066; Fri, 19 Apr 2019 17:54:48 +0000 (GMT) Received: from paulmck-ThinkPad-W541 (unknown [9.70.82.188]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 19 Apr 2019 17:54:48 +0000 (GMT) Received: by paulmck-ThinkPad-W541 (Postfix, from userid 1000) id 9E79916C0A09; Fri, 19 Apr 2019 10:54:50 -0700 (PDT) Date: Fri, 19 Apr 2019 10:54:50 -0700 From: "Paul E. McKenney" To: Alan Stern Cc: LKMM Maintainers -- Akira Yokosawa , Andrea Parri , Boqun Feng , Daniel Lustig , David Howells , Jade Alglave , Luc Maranget , Nicholas Piggin , Peter Zijlstra , Will Deacon , Kernel development list Subject: Re: [PATCH] Documentation: atomic_t.txt: Explain ordering provided by smp_mb__{before,after}_atomic() Reply-To: paulmck@linux.ibm.com References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 19041917-0072-0000-0000-0000041C4AE1 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010957; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000285; SDB=6.01191422; UDB=6.00624405; IPR=6.00972222; MB=3.00026518; MTD=3.00000008; XFM=3.00000015; UTC=2019-04-19 17:54:53 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19041917-0073-0000-0000-00004BE32751 Message-Id: <20190419175450.GC14111@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-19_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1904190129 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 19, 2019 at 01:21:45PM -0400, Alan Stern wrote: > The description of smp_mb__before_atomic() and smp_mb__after_atomic() > in Documentation/atomic_t.txt is slightly terse and misleading. It > does not clearly state that these barriers only affect the ordering of > other instructions with respect to the atomic operation. > > This improves the text to make the actual ordering implications clear, > and also to explain how these barriers differ from a RELEASE or > ACQUIRE ordering. > > Signed-off-by: Alan Stern Queued for further review, thank you, Alan! Thanx, Paul > --- > > > Documentation/atomic_t.txt | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > Index: usb-devel/Documentation/atomic_t.txt > =================================================================== > --- usb-devel.orig/Documentation/atomic_t.txt > +++ usb-devel/Documentation/atomic_t.txt > @@ -171,7 +171,10 @@ The barriers: > smp_mb__{before,after}_atomic() > > only apply to the RMW ops and can be used to augment/upgrade the ordering > -inherent to the used atomic op. These barriers provide a full smp_mb(). > +inherent to the used atomic op. Unlike normal smp_mb() barriers, they order > +only the RMW op itself against the instructions preceding the > +smp_mb__before_atomic() or following the smp_mb__after_atomic(); they do > +not order instructions on the other side of the RMW op at all. > > These helper barriers exist because architectures have varying implicit > ordering on their SMP atomic primitives. For example our TSO architectures > @@ -195,7 +198,8 @@ Further, while something like: > atomic_dec(&X); > > is a 'typical' RELEASE pattern, the barrier is strictly stronger than > -a RELEASE. Similarly for something like: > +a RELEASE because it orders preceding instructions against both the read > +and write parts of the atomic_dec(). Similarly, something like: > > atomic_inc(&X); > smp_mb__after_atomic(); > @@ -227,7 +231,8 @@ strictly stronger than ACQUIRE. As illus > > This should not happen; but a hypothetical atomic_inc_acquire() -- > (void)atomic_fetch_inc_acquire() for instance -- would allow the outcome, > -since then: > +because it would not order the W part of the RMW against the following > +WRITE_ONCE. Thus: > > P1 P2 > >