From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: Re: [PATCH v7 13/27] KVM: arm64/sve: Context switch the SVE registers Date: Thu, 25 Apr 2019 14:35:06 +0100 Message-ID: <20190425133505.GD3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-14-git-send-email-Dave.Martin@arm.com> <20190403200145.c2oep2hbugl7db5t@kamzik.brq.redhat.com> <20190404081008.GY3567@e103592.cambridge.arm.com> <20190404083502.b7a345l2gx3df2zk@kamzik.brq.redhat.com> <20190404083624.GA3567@e103592.cambridge.arm.com> <87d0lbwj63.fsf@zen.linaroharston> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id BA9B34A46F for ; Thu, 25 Apr 2019 09:35:12 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4LHMK2G9cS+P for ; Thu, 25 Apr 2019 09:35:11 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2D3224A36C for ; Thu, 25 Apr 2019 09:35:11 -0400 (EDT) Content-Disposition: inline In-Reply-To: <87d0lbwj63.fsf@zen.linaroharston> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu On Wed, Apr 24, 2019 at 03:51:32PM +0100, Alex Benn=E9e wrote: > = > Dave Martin writes: > = > > On Thu, Apr 04, 2019 at 10:35:02AM +0200, Andrew Jones wrote: > >> On Thu, Apr 04, 2019 at 09:10:08AM +0100, Dave Martin wrote: > >> > On Wed, Apr 03, 2019 at 10:01:45PM +0200, Andrew Jones wrote: > >> > > On Fri, Mar 29, 2019 at 01:00:38PM +0000, Dave Martin wrote: > >> > > > In order to give each vcpu its own view of the SVE registers, th= is > >> > > > patch adds context storage via a new sve_state pointer in struct > >> > > > vcpu_arch. An additional member sve_max_vl is also added for ea= ch > >> > > > vcpu, to determine the maximum vector length visible to the guest > >> > > > and thus the value to be configured in ZCR_EL2.LEN while the vcpu > >> > > > is active. This also determines the layout and size of the stor= age > >> > > > in sve_state, which is read and written by the same backend > >> > > > functions that are used for context-switching the SVE state for > >> > > > host tasks. > >> > > > > >> > > > On SVE-enabled vcpus, SVE access traps are now handled by switch= ing > >> > > > in the vcpu's SVE context and disabling the trap before returning > >> > > > to the guest. On other vcpus, the trap is not handled and an ex= it > >> > > > back to the host occurs, where the handle_sve() fallback path > >> > > > reflects an undefined instruction exception back to the guest, > >> > > > consistently with the behaviour of non-SVE-capable hardware (as = was > >> > > > done unconditionally prior to this patch). > >> > > > > >> > > > No SVE handling is added on non-VHE-only paths, since VHE is an > >> > > > architectural and Kconfig prerequisite of SVE. > >> > > > > >> > > > Signed-off-by: Dave Martin > >> > > > Reviewed-by: Julien Thierry > >> > > > Tested-by: zhang.lei > >> > > > > >> > > > --- > >> > > > > >> > > > Changes since v5: > >> > > > > >> > > > * [Julien Thierry, Julien Grall] Commit message typo fixes > >> > > > > >> > > > * [Mark Rutland] Rename trap_class to hsr_ec, for consistency w= ith > >> > > > existing code. > >> > > > > >> > > > * [Mark Rutland] Simplify condition for refusing to handle an > >> > > > FPSIMD/SVE trap, using multiple if () statements for clarity.= The > >> > > > previous condition was a bit tortuous, and how that the stati= c_key > >> > > > checks have been hoisted out, it makes little difference to t= he > >> > > > compiler how we express the condition here. > >> > > > --- > >> > > > arch/arm64/include/asm/kvm_host.h | 6 ++++ > >> > > > arch/arm64/kvm/fpsimd.c | 5 +-- > >> > > > arch/arm64/kvm/hyp/switch.c | 75 ++++++++++++++++++++++++= +++++---------- > >> > > > 3 files changed, 66 insertions(+), 20 deletions(-) > >> > > > > >> > > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/incl= ude/asm/kvm_host.h > >> > > > index 22cf484..4fabfd2 100644 > >> > > > --- a/arch/arm64/include/asm/kvm_host.h > >> > > > +++ b/arch/arm64/include/asm/kvm_host.h > >> > > > @@ -228,6 +228,8 @@ struct vcpu_reset_state { > >> > > > > >> > > > struct kvm_vcpu_arch { > >> > > > struct kvm_cpu_context ctxt; > >> > > > + void *sve_state; > >> > > > + unsigned int sve_max_vl; > >> > > > > >> > > > /* HYP configuration */ > >> > > > u64 hcr_el2; > >> > > > @@ -323,6 +325,10 @@ struct kvm_vcpu_arch { > >> > > > bool sysregs_loaded_on_cpu; > >> > > > }; > >> > > > > >> > > > +/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ > >> > > > +#define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve= _state) + \ > >> > > > + sve_ffr_offset((vcpu)->arch.sve_max_vl))) > >> > > > >> > > Maybe an inline function instead? > >> > > >> > I tried, but that requires the definition of struct kvm_vcpu to be > >> > visible. I failed to get that here without circular #include proble= ms, > >> > and it looked tricky to fix. > >> > >> Ah, OK > >> > >> > > >> > Since this is a small bit of code which is unlikely to get used by > >> > accident, I decided it was OK to keep it as a macro. > >> > > >> > Can you see another way around this? > >> > >> Nope > > > > OK. If someone eventually solves this, I'd be happy to change to an > > inline function. > = > Is the function intended to be used by more call sites? Currently in the > tree with this plus the v2 fixups I can only see: > = > arch/arm64/include/asm/kvm_host.h:333:#define vcpu_sve_pffr(vcpu) ((voi= d *)((char *)((vcpu)->arch.sve_state) + \ > arch/arm64/kvm/hyp/switch.c:388: sve_load_state(vcpu_sve_pffr(vcpu), Probably not, although it was probably used to save the state back before things were refactored so that fpsimd_save() in arch/arm64/kernel/fpsimd.c is used instead of separate code to save the vcpu state. The expression is ugly so it's nice to abstract it. This also keeps the sve_load_state() call feeling consistent to the equivalent call in task_fpsimd_load() in arm64/kernel/fpsimd.c Other than that, there's no underlying reason for having a macro. Cheers ---Dave From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40260C43218 for ; Thu, 25 Apr 2019 13:35:16 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id B5B99206BF for ; Thu, 25 Apr 2019 13:35:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B5B99206BF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 26E904A476; Thu, 25 Apr 2019 09:35:15 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LpZ9i7Yom5BH; Thu, 25 Apr 2019 09:35:13 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A821F4A477; Thu, 25 Apr 2019 09:35:13 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id BA9B34A46F for ; Thu, 25 Apr 2019 09:35:12 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4LHMK2G9cS+P for ; Thu, 25 Apr 2019 09:35:11 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2D3224A36C for ; Thu, 25 Apr 2019 09:35:11 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E4CAA78; Thu, 25 Apr 2019 06:35:10 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 892903F5C1; Thu, 25 Apr 2019 06:35:08 -0700 (PDT) Date: Thu, 25 Apr 2019 14:35:06 +0100 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH v7 13/27] KVM: arm64/sve: Context switch the SVE registers Message-ID: <20190425133505.GD3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-14-git-send-email-Dave.Martin@arm.com> <20190403200145.c2oep2hbugl7db5t@kamzik.brq.redhat.com> <20190404081008.GY3567@e103592.cambridge.arm.com> <20190404083502.b7a345l2gx3df2zk@kamzik.brq.redhat.com> <20190404083624.GA3567@e103592.cambridge.arm.com> <87d0lbwj63.fsf@zen.linaroharston> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87d0lbwj63.fsf@zen.linaroharston> User-Agent: Mutt/1.5.23 (2014-03-12) Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Message-ID: <20190425133506.jdKuuKccBhsr6iuUTyStq5mQb1sWAV3W00-pq42tDF8@z> On Wed, Apr 24, 2019 at 03:51:32PM +0100, Alex Benn=E9e wrote: > = > Dave Martin writes: > = > > On Thu, Apr 04, 2019 at 10:35:02AM +0200, Andrew Jones wrote: > >> On Thu, Apr 04, 2019 at 09:10:08AM +0100, Dave Martin wrote: > >> > On Wed, Apr 03, 2019 at 10:01:45PM +0200, Andrew Jones wrote: > >> > > On Fri, Mar 29, 2019 at 01:00:38PM +0000, Dave Martin wrote: > >> > > > In order to give each vcpu its own view of the SVE registers, th= is > >> > > > patch adds context storage via a new sve_state pointer in struct > >> > > > vcpu_arch. An additional member sve_max_vl is also added for ea= ch > >> > > > vcpu, to determine the maximum vector length visible to the guest > >> > > > and thus the value to be configured in ZCR_EL2.LEN while the vcpu > >> > > > is active. This also determines the layout and size of the stor= age > >> > > > in sve_state, which is read and written by the same backend > >> > > > functions that are used for context-switching the SVE state for > >> > > > host tasks. > >> > > > > >> > > > On SVE-enabled vcpus, SVE access traps are now handled by switch= ing > >> > > > in the vcpu's SVE context and disabling the trap before returning > >> > > > to the guest. On other vcpus, the trap is not handled and an ex= it > >> > > > back to the host occurs, where the handle_sve() fallback path > >> > > > reflects an undefined instruction exception back to the guest, > >> > > > consistently with the behaviour of non-SVE-capable hardware (as = was > >> > > > done unconditionally prior to this patch). > >> > > > > >> > > > No SVE handling is added on non-VHE-only paths, since VHE is an > >> > > > architectural and Kconfig prerequisite of SVE. > >> > > > > >> > > > Signed-off-by: Dave Martin > >> > > > Reviewed-by: Julien Thierry > >> > > > Tested-by: zhang.lei > >> > > > > >> > > > --- > >> > > > > >> > > > Changes since v5: > >> > > > > >> > > > * [Julien Thierry, Julien Grall] Commit message typo fixes > >> > > > > >> > > > * [Mark Rutland] Rename trap_class to hsr_ec, for consistency w= ith > >> > > > existing code. > >> > > > > >> > > > * [Mark Rutland] Simplify condition for refusing to handle an > >> > > > FPSIMD/SVE trap, using multiple if () statements for clarity.= The > >> > > > previous condition was a bit tortuous, and how that the stati= c_key > >> > > > checks have been hoisted out, it makes little difference to t= he > >> > > > compiler how we express the condition here. > >> > > > --- > >> > > > arch/arm64/include/asm/kvm_host.h | 6 ++++ > >> > > > arch/arm64/kvm/fpsimd.c | 5 +-- > >> > > > arch/arm64/kvm/hyp/switch.c | 75 ++++++++++++++++++++++++= +++++---------- > >> > > > 3 files changed, 66 insertions(+), 20 deletions(-) > >> > > > > >> > > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/incl= ude/asm/kvm_host.h > >> > > > index 22cf484..4fabfd2 100644 > >> > > > --- a/arch/arm64/include/asm/kvm_host.h > >> > > > +++ b/arch/arm64/include/asm/kvm_host.h > >> > > > @@ -228,6 +228,8 @@ struct vcpu_reset_state { > >> > > > > >> > > > struct kvm_vcpu_arch { > >> > > > struct kvm_cpu_context ctxt; > >> > > > + void *sve_state; > >> > > > + unsigned int sve_max_vl; > >> > > > > >> > > > /* HYP configuration */ > >> > > > u64 hcr_el2; > >> > > > @@ -323,6 +325,10 @@ struct kvm_vcpu_arch { > >> > > > bool sysregs_loaded_on_cpu; > >> > > > }; > >> > > > > >> > > > +/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ > >> > > > +#define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve= _state) + \ > >> > > > + sve_ffr_offset((vcpu)->arch.sve_max_vl))) > >> > > > >> > > Maybe an inline function instead? > >> > > >> > I tried, but that requires the definition of struct kvm_vcpu to be > >> > visible. I failed to get that here without circular #include proble= ms, > >> > and it looked tricky to fix. > >> > >> Ah, OK > >> > >> > > >> > Since this is a small bit of code which is unlikely to get used by > >> > accident, I decided it was OK to keep it as a macro. > >> > > >> > Can you see another way around this? > >> > >> Nope > > > > OK. If someone eventually solves this, I'd be happy to change to an > > inline function. > = > Is the function intended to be used by more call sites? Currently in the > tree with this plus the v2 fixups I can only see: > = > arch/arm64/include/asm/kvm_host.h:333:#define vcpu_sve_pffr(vcpu) ((voi= d *)((char *)((vcpu)->arch.sve_state) + \ > arch/arm64/kvm/hyp/switch.c:388: sve_load_state(vcpu_sve_pffr(vcpu), Probably not, although it was probably used to save the state back before things were refactored so that fpsimd_save() in arch/arm64/kernel/fpsimd.c is used instead of separate code to save the vcpu state. The expression is ugly so it's nice to abstract it. This also keeps the sve_load_state() call feeling consistent to the equivalent call in task_fpsimd_load() in arm64/kernel/fpsimd.c Other than that, there's no underlying reason for having a macro. Cheers ---Dave _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AEF4C43219 for ; Thu, 25 Apr 2019 13:35:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4091D206BF for ; Thu, 25 Apr 2019 13:35:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZSu4t3YI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4091D206BF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BAS5EStilF106yqoE7eKs/vY6onl2UZDERaQTNLaMR8=; b=ZSu4t3YI7zJBhA 0NCCHQPKWHR2cAaih+DjfkSWmeKsPqRuENUkfWGBx8VOadhjmCoKCUsVu03J2msMrrjIW4b2jBwqb K1Ssfs0WZgkoUPTaQaYyiwVO2G/rrH0w+07YxyyhQvsq4CA6YXfnJlyIkkwoDU4um4Mwjn+zZO260 vqtiNuJ/992FuJ5LEmhya0Kh5Yka+L+iWWTTinWPpYgwyFto2qxkAdANxAaIPbDX8hQoP5bYbvVs8 n5S3yMeKtitYb+lEKw29xeuPghOAA0FHnVYfnsgo0CNXEcPqFNqH1aBQyVqEXNuAAy18oxmEwZiX4 p8kpasvfdcOjMJZ/1F0g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJeXZ-0000hp-97; Thu, 25 Apr 2019 13:35:53 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJeWt-00083l-4J for linux-arm-kernel@lists.infradead.org; Thu, 25 Apr 2019 13:35:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E4CAA78; Thu, 25 Apr 2019 06:35:10 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 892903F5C1; Thu, 25 Apr 2019 06:35:08 -0700 (PDT) Date: Thu, 25 Apr 2019 14:35:06 +0100 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH v7 13/27] KVM: arm64/sve: Context switch the SVE registers Message-ID: <20190425133505.GD3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-14-git-send-email-Dave.Martin@arm.com> <20190403200145.c2oep2hbugl7db5t@kamzik.brq.redhat.com> <20190404081008.GY3567@e103592.cambridge.arm.com> <20190404083502.b7a345l2gx3df2zk@kamzik.brq.redhat.com> <20190404083624.GA3567@e103592.cambridge.arm.com> <87d0lbwj63.fsf@zen.linaroharston> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87d0lbwj63.fsf@zen.linaroharston> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_063511_856598_1EF9E63E X-CRM114-Status: GOOD ( 34.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 24, 2019 at 03:51:32PM +0100, Alex Benn=E9e wrote: > = > Dave Martin writes: > = > > On Thu, Apr 04, 2019 at 10:35:02AM +0200, Andrew Jones wrote: > >> On Thu, Apr 04, 2019 at 09:10:08AM +0100, Dave Martin wrote: > >> > On Wed, Apr 03, 2019 at 10:01:45PM +0200, Andrew Jones wrote: > >> > > On Fri, Mar 29, 2019 at 01:00:38PM +0000, Dave Martin wrote: > >> > > > In order to give each vcpu its own view of the SVE registers, th= is > >> > > > patch adds context storage via a new sve_state pointer in struct > >> > > > vcpu_arch. An additional member sve_max_vl is also added for ea= ch > >> > > > vcpu, to determine the maximum vector length visible to the guest > >> > > > and thus the value to be configured in ZCR_EL2.LEN while the vcpu > >> > > > is active. This also determines the layout and size of the stor= age > >> > > > in sve_state, which is read and written by the same backend > >> > > > functions that are used for context-switching the SVE state for > >> > > > host tasks. > >> > > > > >> > > > On SVE-enabled vcpus, SVE access traps are now handled by switch= ing > >> > > > in the vcpu's SVE context and disabling the trap before returning > >> > > > to the guest. On other vcpus, the trap is not handled and an ex= it > >> > > > back to the host occurs, where the handle_sve() fallback path > >> > > > reflects an undefined instruction exception back to the guest, > >> > > > consistently with the behaviour of non-SVE-capable hardware (as = was > >> > > > done unconditionally prior to this patch). > >> > > > > >> > > > No SVE handling is added on non-VHE-only paths, since VHE is an > >> > > > architectural and Kconfig prerequisite of SVE. > >> > > > > >> > > > Signed-off-by: Dave Martin > >> > > > Reviewed-by: Julien Thierry > >> > > > Tested-by: zhang.lei > >> > > > > >> > > > --- > >> > > > > >> > > > Changes since v5: > >> > > > > >> > > > * [Julien Thierry, Julien Grall] Commit message typo fixes > >> > > > > >> > > > * [Mark Rutland] Rename trap_class to hsr_ec, for consistency w= ith > >> > > > existing code. > >> > > > > >> > > > * [Mark Rutland] Simplify condition for refusing to handle an > >> > > > FPSIMD/SVE trap, using multiple if () statements for clarity.= The > >> > > > previous condition was a bit tortuous, and how that the stati= c_key > >> > > > checks have been hoisted out, it makes little difference to t= he > >> > > > compiler how we express the condition here. > >> > > > --- > >> > > > arch/arm64/include/asm/kvm_host.h | 6 ++++ > >> > > > arch/arm64/kvm/fpsimd.c | 5 +-- > >> > > > arch/arm64/kvm/hyp/switch.c | 75 ++++++++++++++++++++++++= +++++---------- > >> > > > 3 files changed, 66 insertions(+), 20 deletions(-) > >> > > > > >> > > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/incl= ude/asm/kvm_host.h > >> > > > index 22cf484..4fabfd2 100644 > >> > > > --- a/arch/arm64/include/asm/kvm_host.h > >> > > > +++ b/arch/arm64/include/asm/kvm_host.h > >> > > > @@ -228,6 +228,8 @@ struct vcpu_reset_state { > >> > > > > >> > > > struct kvm_vcpu_arch { > >> > > > struct kvm_cpu_context ctxt; > >> > > > + void *sve_state; > >> > > > + unsigned int sve_max_vl; > >> > > > > >> > > > /* HYP configuration */ > >> > > > u64 hcr_el2; > >> > > > @@ -323,6 +325,10 @@ struct kvm_vcpu_arch { > >> > > > bool sysregs_loaded_on_cpu; > >> > > > }; > >> > > > > >> > > > +/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ > >> > > > +#define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve= _state) + \ > >> > > > + sve_ffr_offset((vcpu)->arch.sve_max_vl))) > >> > > > >> > > Maybe an inline function instead? > >> > > >> > I tried, but that requires the definition of struct kvm_vcpu to be > >> > visible. I failed to get that here without circular #include proble= ms, > >> > and it looked tricky to fix. > >> > >> Ah, OK > >> > >> > > >> > Since this is a small bit of code which is unlikely to get used by > >> > accident, I decided it was OK to keep it as a macro. > >> > > >> > Can you see another way around this? > >> > >> Nope > > > > OK. If someone eventually solves this, I'd be happy to change to an > > inline function. > = > Is the function intended to be used by more call sites? Currently in the > tree with this plus the v2 fixups I can only see: > = > arch/arm64/include/asm/kvm_host.h:333:#define vcpu_sve_pffr(vcpu) ((voi= d *)((char *)((vcpu)->arch.sve_state) + \ > arch/arm64/kvm/hyp/switch.c:388: sve_load_state(vcpu_sve_pffr(vcpu), Probably not, although it was probably used to save the state back before things were refactored so that fpsimd_save() in arch/arm64/kernel/fpsimd.c is used instead of separate code to save the vcpu state. The expression is ugly so it's nice to abstract it. This also keeps the sve_load_state() call feeling consistent to the equivalent call in task_fpsimd_load() in arm64/kernel/fpsimd.c Other than that, there's no underlying reason for having a macro. Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel