All of lore.kernel.org
 help / color / mirror / Atom feed
From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 17/50] x86: broadwell: Allow SDRAM init from SPL
Date: Thu, 25 Apr 2019 21:58:49 -0600	[thread overview]
Message-ID: <20190426035922.20596-18-sjg@chromium.org> (raw)
In-Reply-To: <20190426035922.20596-1-sjg@chromium.org>

At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Update commit message to make it clear this patch is just for broadwell
- Bring in sdram_console_tx_byte() to allow debugging

 arch/x86/cpu/broadwell/Makefile      |   2 +-
 arch/x86/cpu/broadwell/northbridge.c | 100 +++++++++++++++++++++++++++
 arch/x86/cpu/broadwell/sdram.c       |  93 -------------------------
 3 files changed, 101 insertions(+), 94 deletions(-)

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index d3785aabdf2..d464507e6c0 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -13,4 +13,4 @@ obj-y += pinctrl_broadwell.o
 obj-y += power_state.o
 obj-y += refcode.o
 obj-y += sata.o
-obj-y += sdram.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o
diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c
index 3055880bb77..4bcab785560 100644
--- a/arch/x86/cpu/broadwell/northbridge.c
+++ b/arch/x86/cpu/broadwell/northbridge.c
@@ -6,8 +6,108 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/io.h>
+#include <asm/mrc_common.h>
 #include <asm/arch/iomap.h>
 #include <asm/arch/pch.h>
+#include <asm/arch/pei_data.h>
+
+__weak asmlinkage void sdram_console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+	putc(byte);
+#endif
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->pei_version = PEI_VERSION;
+	pei_data->board_type = BOARD_TYPE_ULT;
+	pei_data->pciexbar = MCFG_BASE_ADDRESS;
+	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+	pei_data->ehcibar = EARLY_EHCI_BAR;
+	pei_data->xhcibar = EARLY_XHCI_BAR;
+	pei_data->gttbar = EARLY_GTT_BAR;
+	pei_data->pmbase = ACPI_BASE_ADDRESS;
+	pei_data->gpiobase = GPIO_BASE_ADDRESS;
+	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+	pei_data->tx_byte = sdram_console_tx_byte;
+	pei_data->ddr_refresh_2x = 1;
+}
+
+static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length,
+			       uint enable, uint oc_pin, uint location)
+{
+	pei_data->usb2_ports[port].length   = length;
+	pei_data->usb2_ports[port].enable   = enable;
+	pei_data->usb2_ports[port].oc_pin   = oc_pin;
+	pei_data->usb2_ports[port].location = location;
+}
+
+static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable,
+			       uint oc_pin, uint fixed_eq)
+{
+	pei_data->usb3_ports[port].enable   = enable;
+	pei_data->usb3_ports[port].oc_pin   = oc_pin;
+	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	/* DQ byte map for Samus board */
+	const u8 dq_map[2][6][2] = {
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+	/* DQS CPU<>DRAM map for Samus board */
+	const u8 dqs_map[2][8] = {
+		{ 2, 0, 1, 3, 6, 4, 7, 5 },
+		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+	pei_data->ec_present = 1;
+
+	/* One installed DIMM per channel */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+	/* P0: HOST PORT */
+	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+			   USB_PORT_BACK_PANEL);
+	/* P1: HOST PORT */
+	pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+			   USB_PORT_BACK_PANEL);
+	/* P2: RAIDEN */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P3: SD CARD */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P4: RAIDEN */
+	pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P5: WWAN (Disabled) */
+	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P6: CAMERA */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: BT */
+	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+
+	/* P1: HOST PORT */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: HOST PORT */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: RAIDEN */
+	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+	/* P4: RAIDEN */
+	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
 
 static int broadwell_northbridge_early_init(struct udevice *dev)
 {
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 1b9f9840c6f..b8450cc9d29 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -34,99 +34,6 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void broadwell_fill_pei_data(struct pei_data *pei_data)
-{
-	pei_data->pei_version = PEI_VERSION;
-	pei_data->board_type = BOARD_TYPE_ULT;
-	pei_data->pciexbar = MCFG_BASE_ADDRESS;
-	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
-	pei_data->ehcibar = EARLY_EHCI_BAR;
-	pei_data->xhcibar = EARLY_XHCI_BAR;
-	pei_data->gttbar = EARLY_GTT_BAR;
-	pei_data->pmbase = ACPI_BASE_ADDRESS;
-	pei_data->gpiobase = GPIO_BASE_ADDRESS;
-	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
-	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
-	pei_data->tx_byte = sdram_console_tx_byte;
-	pei_data->ddr_refresh_2x = 1;
-}
-
-static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
-				      uint16_t length, uint8_t enable,
-				      uint8_t oc_pin, uint8_t location)
-{
-	pei_data->usb2_ports[port].length   = length;
-	pei_data->usb2_ports[port].enable   = enable;
-	pei_data->usb2_ports[port].oc_pin   = oc_pin;
-	pei_data->usb2_ports[port].location = location;
-}
-
-static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
-				      uint8_t enable, uint8_t oc_pin,
-				      uint8_t fixed_eq)
-{
-	pei_data->usb3_ports[port].enable   = enable;
-	pei_data->usb3_ports[port].oc_pin   = oc_pin;
-	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
-}
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
-	/* DQ byte map for Samus board */
-	const u8 dq_map[2][6][2] = {
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
-	/* DQS CPU<>DRAM map for Samus board */
-	const u8 dqs_map[2][8] = {
-		{ 2, 0, 1, 3, 6, 4, 7, 5 },
-		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
-
-	pei_data->ec_present = 1;
-
-	/* One installed DIMM per channel */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
-	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
-	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-
-	/* P0: HOST PORT */
-	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
-			   USB_PORT_BACK_PANEL);
-	/* P1: HOST PORT */
-	pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
-			   USB_PORT_BACK_PANEL);
-	/* P2: RAIDEN */
-	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_BACK_PANEL);
-	/* P3: SD CARD */
-	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-	/* P4: RAIDEN */
-	pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_BACK_PANEL);
-	/* P5: WWAN (Disabled) */
-	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
-			   USB_PORT_SKIP);
-	/* P6: CAMERA */
-	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-	/* P7: BT */
-	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
-			   USB_PORT_INTERNAL);
-
-	/* P1: HOST PORT */
-	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
-	/* P2: HOST PORT */
-	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
-	/* P3: RAIDEN */
-	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
-	/* P4: RAIDEN */
-	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
-}
-
 static unsigned long get_top_of_ram(struct udevice *dev)
 {
 	/*
-- 
2.21.0.593.g511ec345e18-goog

  parent reply	other threads:[~2019-04-26  3:58 UTC|newest]

Thread overview: 113+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-26  3:58 [U-Boot] [PATCH v2 00/50] x86: Add support for booting from TPL Simon Glass
2019-04-26  3:58 ` [U-Boot] [PATCH v2 01/50] binman: Don't generate an error in 'text' entry constructor Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 02/50] binman: Don't show image-skip message by default Simon Glass
2019-05-01 11:59   ` Bin Meng
2019-05-01 15:16     ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 03/50] binman: Add a missing comment in Entry_vblock Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 04/50] dm: core: Fix translate condition in ofnode_get_addr_size() Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 05/50] cros_ec: Use a hyphen in the uclass name Simon Glass
2019-05-01 12:00   ` Bin Meng
2019-05-02 16:53     ` Simon Glass
2019-04-26  3:58 ` [U-Boot] [PATCH v2 06/50] spl: Allow sandbox to build a device-tree file Simon Glass
2019-05-01 12:13   ` Bin Meng
2019-05-01 15:16     ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 07/50] binman: Allow sections to have an offset Simon Glass
2019-05-01 12:13   ` Bin Meng
2019-05-01 15:16     ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 08/50] x86: start64: Fix copyright message Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 09/50] x86: mp_init: Use proper error numbers Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 10/50] x86: Add a way to reinit the cpu Simon Glass
2019-05-01 15:16   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 11/50] x86: dts: Add device-tree labels for rtc and reset Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 12/50] x86: Update a stale comment about ifdtool Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 13/50] x86: Support SPL and TPL Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 14/50] x86: Support booting with TPL Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 15/50] x86: Add a handoff header file Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 16/50] x86: broadwell: Improve SDRAM debugging output Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` Simon Glass [this message]
2019-05-01 13:03   ` [U-Boot] [PATCH v2 17/50] x86: broadwell: Allow SDRAM init from SPL Bin Meng
2019-05-01 15:25     ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 18/50] x86: Move init of debug UART to cpu.c Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 19/50] x86: broadwell: Split CPU init Simon Glass
2019-05-01 15:25   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 20/50] x86: Add support for starting from SPL/TPL Simon Glass
2019-05-01 13:03   ` Bin Meng
2019-05-01 15:25     ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 21/50] x86: Allow 16-bit init to be in TPL Simon Glass
2019-05-01 15:34   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 22/50] x86: broadwell: Allow booting from SPL Simon Glass
2019-05-01 15:34   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 23/50] x86: broadwell: Select refcode and CPU code for SPL Simon Glass
2019-05-01 15:35   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 24/50] x86: Add common Intel " Simon Glass
2019-05-01 15:35   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 25/50] x86: Support saving MRC data from SPL Simon Glass
2019-05-01 15:35   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 26/50] x86: Add a simple TPL implementation Simon Glass
2019-05-01 15:35   ` Bin Meng
2019-04-26  3:58 ` [U-Boot] [PATCH v2 27/50] x86: mrccache: Add more debugging Simon Glass
2019-05-01 15:35   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 28/50] x86: sysreset: Separate out the EFI code Simon Glass
2019-05-01 13:42   ` Bin Meng
2019-05-01 18:56     ` Heinrich Schuchardt
2019-04-26  3:59 ` [U-Boot] [PATCH v2 29/50] x86: pch: Add an ioctl to read power-management info Simon Glass
2019-05-01 13:42   ` Bin Meng
2019-05-01 15:43     ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 30/50] x86: ivybridge: Implement PCH_REQ_PMBASE_INFO Simon Glass
2019-05-01 13:42   ` Bin Meng
2019-05-01 15:43     ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 31/50] x86: broadwell: " Simon Glass
2019-05-01 14:50   ` Bin Meng
2019-05-01 15:43     ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 32/50] x86: sysreset: Implement power-off if available Simon Glass
2019-05-01 14:50   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 33/50] x86: Support TPL in Intel common code Simon Glass
2019-05-01 15:44   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 34/50] x86: Don't set up MTRRs in SPL Simon Glass
2019-05-01 15:44   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 35/50] x86: Don't generate a bootstage report " Simon Glass
2019-05-01 15:44   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 36/50] x86: Support PCI VGA ROM when TPL is used Simon Glass
2019-05-01 15:44   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 37/50] x86: sysreset: Implement the get_last() method Simon Glass
2019-05-01 15:48   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 38/50] x86: Add documention on the samus flashmap Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 39/50] x86: samus: Update device tree for SPL Simon Glass
2019-05-01 15:52   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 40/50] x86: samus: Update device tree for verified boot Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 41/50] x86: Update device tree for TPL Simon Glass
2019-05-01 16:00   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 42/50] x86: Update device tree for Chromium OS verified boot Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 43/50] x86: Fix device-tree indentation Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 44/50] x86: samus: Increase the pre-reloc memory again Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 45/50] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" Simon Glass
2019-05-01 16:09   ` Bin Meng
2019-05-02  9:24     ` Thierry Reding
2019-05-02 16:22       ` Simon Glass
2019-05-07  9:28         ` Bin Meng
2019-05-08  3:04           ` Simon Glass
2019-05-08  3:25             ` Bin Meng
2019-05-09 15:34             ` Thierry Reding
2019-04-26  3:59 ` [U-Boot] [PATCH v2 46/50] x86: Enable the RTC on all boards Simon Glass
2019-05-01 16:17   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 47/50] x86: Update the memory map a little Simon Glass
2019-05-01 16:17   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 48/50] x86: broadwell: Update PCH to work in TPL Simon Glass
2019-05-01 16:17   ` Bin Meng
2019-04-26  3:59 ` [U-Boot] [PATCH v2 49/50] x86: Add a way to jump from TPL to SPL Simon Glass
2019-05-01 16:17   ` Bin Meng
2019-05-02 16:53     ` Simon Glass
2019-04-26  3:59 ` [U-Boot] [PATCH v2 50/50] x86: samus: Add a target to boot through TPL Simon Glass
2019-05-01 16:20 ` [U-Boot] [PATCH v2 00/50] x86: Add support for booting from TPL Bin Meng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190426035922.20596-18-sjg@chromium.org \
    --to=sjg@chromium.org \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.