From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Thu, 25 Apr 2019 21:59:02 -0600 Subject: [U-Boot] [PATCH v2 30/50] x86: ivybridge: Implement PCH_REQ_PMBASE_INFO In-Reply-To: <20190426035922.20596-1-sjg@chromium.org> References: <20190426035922.20596-1-sjg@chromium.org> Message-ID: <20190426035922.20596-31-sjg@chromium.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Implement this ioctl() to support power off. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to implement PCH_REQ_PMBASE_INFO on ivybridge arch/x86/cpu/ivybridge/bd82x6x.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index ed9bce64168..1cb6cecda9e 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -229,6 +229,21 @@ static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data, return -ENOENT; return val & RCBA_AUDIO_CONFIG_MASK; + case PCH_REQ_PMBASE_INFO: { + struct pch_pmbase_info *pm = data; + int ret; + + /* Find the base address of the powermanagement registers */ + ret = dm_pci_read_config16(dev, 0x40, &pm->base); + if (ret) + return ret; + pm->base &= 0xfffe; + pm->gpio0_en_ofs = GPE0_EN; + pm->pm1_sts_ofs = PM1_STS; + pm->pm1_cnt_ofs = PM1_CNT; + + return 0; + } default: return -ENOSYS; } -- 2.21.0.593.g511ec345e18-goog