From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Thu, 25 Apr 2019 21:59:03 -0600 Subject: [U-Boot] [PATCH v2 31/50] x86: broadwell: Implement PCH_REQ_PMBASE_INFO In-Reply-To: <20190426035922.20596-1-sjg@chromium.org> References: <20190426035922.20596-1-sjg@chromium.org> Message-ID: <20190426035922.20596-32-sjg@chromium.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Implement this ioctl() to support power off. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch to implement PCH_REQ_PMBASE_INFO on broadwell arch/x86/cpu/broadwell/pch.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 73d3d3b5154..e61efa7b16c 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -630,10 +630,35 @@ static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep) return 0; } +static int broadwell_ioctl(struct udevice *dev, enum pch_req_t req, void *data, + int size) +{ + switch (req) { + case PCH_REQ_PMBASE_INFO: { + struct pch_pmbase_info *pm = data; + int ret; + + /* Find the base address of the powermanagement registers */ + ret = dm_pci_read_config16(dev, 0x40, &pm->base); + if (ret) + return ret; + pm->base &= 0xfffe; + pm->gpio0_en_ofs = GPE0_EN(0); + pm->pm1_sts_ofs = PM1_STS; + pm->pm1_cnt_ofs = PM1_CNT; + + return 0; + } + default: + return -ENOSYS; + } +} + static const struct pch_ops broadwell_pch_ops = { .get_spi_base = broadwell_pch_get_spi_base, .set_spi_protect = broadwell_set_spi_protect, .get_gpio_base = broadwell_get_gpio_base, + .ioctl = broadwell_ioctl, }; static const struct udevice_id broadwell_pch_ids[] = { -- 2.21.0.593.g511ec345e18-goog