From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [2/2] dmaengine: milbeaut: Add Milbeaut AXI DMA controller From: Vinod Koul Message-Id: <20190426114629.GU28103@vkoul-mobl> Date: Fri, 26 Apr 2019 17:16:29 +0530 To: Kazuhiro Kasai Cc: robh+dt@kernel.org, mark.rutland@arm.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, orito.takao@socionext.com, sugaya.taichi@socionext.com, kanematsu.shinji@socionext.com, jaswinder.singh@linaro.org, masami.hiramatsu@linaro.org, linux-kernel@vger.kernel.org List-ID: T24gMjUtMDMtMTksIDEzOjE1LCBLYXp1aGlybyBLYXNhaSB3cm90ZToKPiBBZGQgTWlsYmVhdXQg QVhJIERNQSBjb250cm9sbGVyLiBUaGlzIERNQSBjb250cm9sbGVyIGhhcwo+IG9ubHkgY2FwYWJs ZSBvZiBtZW1vcnkgdG8gbWVtb3J5IHRyYW5zZmVyLgoKSGF2ZSB5b3UgdGVzdGVkIHRoaXMgd2l0 aCBkbWF0ZXN0PwoKPiArc3RydWN0IG0xMHZfZG1hX2NoYW4gewo+ICsJc3RydWN0IGRtYV9jaGFu IGNoYW47Cj4gKwlzdHJ1Y3QgbTEwdl9kbWFfZGV2aWNlICptZG1hYzsKPiArCXZvaWQgX19pb21l bSAqcmVnczsKPiArCWludCBpcnE7Cj4gKwlzdHJ1Y3QgbTEwdl9kbWFfZGVzYyBtZGVzYzsKClNv IHRoZXJlIGlzIGEgKnNpbmdsZSogZGVzY3JpcHRvcj8gTm90IGEgbGlzdD8/Cgo+ICtzdGF0aWMg dm9pZCBtMTB2X3hkbWFjX2Rpc2FibGVfZG1hKHN0cnVjdCBtMTB2X2RtYV9kZXZpY2UgKm1kbWFj KQo+ICt7Cj4gKwl1bnNpZ25lZCBpbnQgdmFsOwo+ICsKPiArCXZhbCA9IHJlYWRsKG1kbWFjLT5y ZWdzICsgTTEwVl9YREFDUyk7Cj4gKwl2YWwgJj0gfk0xMFZfWERBQ1NfWEU7Cj4gKwl2YWwgfD0g RklFTERfUFJFUChNMTBWX1hEQUNTX1hFLCAwKTsKPiArCXdyaXRlbCh2YWwsIG1kbWFjLT5yZWdz ICsgTTEwVl9YREFDUyk7CgpXaHkgbm90IGNyZWF0ZSBhIG1vZGlmeWwoKSBtYWNybyBhbmQgdXNl IGl0IGhlcmUKCj4gK3N0YXRpYyB2b2lkIG0xMHZfeGRtYWNfaXNzdWVfcGVuZGluZyhzdHJ1Y3Qg ZG1hX2NoYW4gKmNoYW4pCj4gK3sKPiArCXN0cnVjdCBtMTB2X2RtYV9jaGFuICptY2hhbiA9IHRv X20xMHZfZG1hX2NoYW4oY2hhbik7Cj4gKwo+ICsJbTEwdl94ZG1hY19jb25maWdfY2hhbihtY2hh bik7Cj4gKwo+ICsJbTEwdl94ZG1hY19lbmFibGVfY2hhbihtY2hhbik7CgpZb3UgZG9udCBjaGVj ayBpZiBhbnl0aGluZyBpcyBhbHJlYWR5IHJ1bm5pbmcgb3Igbm90PwoKPiArc3RhdGljIGRtYV9j b29raWVfdCBtMTB2X3hkbWFjX3R4X3N1Ym1pdChzdHJ1Y3QgZG1hX2FzeW5jX3R4X2Rlc2NyaXB0 b3IgKnR4ZCkKPiArewo+ICsJc3RydWN0IG0xMHZfZG1hX2NoYW4gKm1jaGFuID0gdG9fbTEwdl9k bWFfY2hhbih0eGQtPmNoYW4pOwo+ICsJZG1hX2Nvb2tpZV90IGNvb2tpZTsKPiArCXVuc2lnbmVk IGxvbmcgZmxhZ3M7Cj4gKwo+ICsJc3Bpbl9sb2NrX2lycXNhdmUoJm1jaGFuLT5sb2NrLCBmbGFn cyk7Cj4gKwljb29raWUgPSBkbWFfY29va2llX2Fzc2lnbih0eGQpOwo+ICsJc3Bpbl91bmxvY2tf aXJxcmVzdG9yZSgmbWNoYW4tPmxvY2ssIGZsYWdzKTsKPiArCj4gKwlyZXR1cm4gY29va2llOwoK c291bmRzIGxpa2UgdmNoYW5fdHhfc3VibWl0KCkgaSB0aGluayB5b3UgY2FuIHVzZSB2aXJ0LWRt YSBsYXllciBhbmQgdGhlbgpnZXQgcmlkIG9mIGFydGlmaWNpYWwgbGltaXQgaW4gZHJpdmVyIGFu ZCBiZSBhYmxlIHRvIHF1ZXVlIHVwIHRoZSB0eG4gb24KZG1hZW5naW5lLgoKPiArc3RhdGljIHN0 cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqCj4gK20xMHZfeGRtYWNfcHJlcF9kbWFfbWVt Y3B5KHN0cnVjdCBkbWFfY2hhbiAqY2hhbiwgZG1hX2FkZHJfdCBkc3QsCj4gKwkJCSAgIGRtYV9h ZGRyX3Qgc3JjLCBzaXplX3QgbGVuLCB1bnNpZ25lZCBsb25nIGZsYWdzKQo+ICt7Cj4gKwlzdHJ1 Y3QgbTEwdl9kbWFfY2hhbiAqbWNoYW4gPSB0b19tMTB2X2RtYV9jaGFuKGNoYW4pOwo+ICsKPiAr CWRtYV9hc3luY190eF9kZXNjcmlwdG9yX2luaXQoJm1jaGFuLT5tZGVzYy50eGQsIGNoYW4pOwo+ ICsJbWNoYW4tPm1kZXNjLnR4ZC50eF9zdWJtaXQgPSBtMTB2X3hkbWFjX3R4X3N1Ym1pdDsKPiAr CW1jaGFuLT5tZGVzYy50eGQuY2FsbGJhY2sgPSBOVUxMOwo+ICsJbWNoYW4tPm1kZXNjLnR4ZC5m bGFncyA9IGZsYWdzOwo+ICsJbWNoYW4tPm1kZXNjLnR4ZC5jb29raWUgPSAtRUJVU1k7Cj4gKwo+ ICsJbWNoYW4tPm1kZXNjLmxlbiA9IGxlbjsKPiArCW1jaGFuLT5tZGVzYy5zcmMgPSBzcmM7Cj4g KwltY2hhbi0+bWRlc2MuZHN0ID0gZHN0Owo+ICsKPiArCXJldHVybiAmbWNoYW4tPm1kZXNjLnR4 ZDsKClNvIHlvdSBzdXBwb3J0IHNpbmdsZSBkZXNjcmlwdG9yIGFuZCBkb250IGNoZWNrIGlmIHRo aXMgaGFzIGJlZW4gYWxyZWFkeQpjb25maWd1cmVkLiBTbyBJIGd1ZXNzIHRoaXMgaGFzIGJlZW4g dGVzdGVkIGJ5IGRvaW5nIHR4biBvbmUgYXQgYSB0aW1lCmFuZCBub3Qgc3VibWl0dGVkIGJ1bmNo IG9mIHR4biBhbmQgd2FpdCBmb3IgdGhlbSB0byBjb21wbGV0ZS4gUGxlYXNlIGZpeAp0aGF0IHRv IHJlYWxseSBlbmFibGUgZG1hZW5naW5lIGNhcGFiaWxpdGllcy4KCj4gK3N0YXRpYyBpbnQgbTEw dl94ZG1hY19yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3Ry dWN0IG0xMHZfZG1hX2NoYW4gKm1jaGFuOwo+ICsJc3RydWN0IG0xMHZfZG1hX2RldmljZSAqbWRt YWMgPSBwbGF0Zm9ybV9nZXRfZHJ2ZGF0YShwZGV2KTsKPiArCWludCBpOwo+ICsKPiArCW0xMHZf eGRtYWNfZGlzYWJsZV9kbWEobWRtYWMpOwo+ICsKPiArCWZvciAoaSA9IDA7IGkgPCBtZG1hYy0+ Y2hhbm5lbHM7IGkrKykgewo+ICsJCW1jaGFuID0gJm1kbWFjLT5tY2hhbltpXTsKPiArCQlkZXZt X2ZyZWVfaXJxKCZwZGV2LT5kZXYsIG1jaGFuLT5pcnEsIG1jaGFuKTsKPiArCX0KCk5vIGNhbGwg dG8gZG1hX2FzeW5jX2RldmljZV91bnJlZ2lzdGVyKCk/Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_PASS,T_DKIMWL_WL_HIGH,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D51BC43219 for ; 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Fri, 26 Apr 2019 11:46:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1556279195; bh=n8yw9/htPFOd154d9bBPo0Nohz8yCfSxy7/DyQypKE4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ygvk7YrxZCWvJLv7BTONpvongXp0h3FGxAc0sYzoNI1080pCCZhPHxuxPptYmJG2S G9Kf12BKMGEm3TNUPVfqwjKiVI5kSrny5ANfb9W8ekK4E0P3i+m4f6yallRSSYVYW0 FAx08FZTHfpmPT1kxXZ/fmHQ3QkFFzuvCFMjQA2Q= Date: Fri, 26 Apr 2019 17:16:29 +0530 From: Vinod Koul To: Kazuhiro Kasai Cc: robh+dt@kernel.org, mark.rutland@arm.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, orito.takao@socionext.com, sugaya.taichi@socionext.com, kanematsu.shinji@socionext.com, jaswinder.singh@linaro.org, masami.hiramatsu@linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] dmaengine: milbeaut: Add Milbeaut AXI DMA controller Message-ID: <20190426114629.GU28103@vkoul-mobl> References: <1553487314-9185-1-git-send-email-kasai.kazuhiro@socionext.com> <1553487314-9185-3-git-send-email-kasai.kazuhiro@socionext.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline In-Reply-To: <1553487314-9185-3-git-send-email-kasai.kazuhiro@socionext.com> User-Agent: Mutt/1.11.3 (2019-02-01) Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190426114629.yY06RJgqD6U-7gEoe5rTDIOYJ0aOna0o5agZDluu1Q8@z> On 25-03-19, 13:15, Kazuhiro Kasai wrote: > Add Milbeaut AXI DMA controller. This DMA controller has > only capable of memory to memory transfer. Have you tested this with dmatest? > +struct m10v_dma_chan { > + struct dma_chan chan; > + struct m10v_dma_device *mdmac; > + void __iomem *regs; > + int irq; > + struct m10v_dma_desc mdesc; So there is a *single* descriptor? Not a list?? > +static void m10v_xdmac_disable_dma(struct m10v_dma_device *mdmac) > +{ > + unsigned int val; > + > + val = readl(mdmac->regs + M10V_XDACS); > + val &= ~M10V_XDACS_XE; > + val |= FIELD_PREP(M10V_XDACS_XE, 0); > + writel(val, mdmac->regs + M10V_XDACS); Why not create a modifyl() macro and use it here > +static void m10v_xdmac_issue_pending(struct dma_chan *chan) > +{ > + struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan); > + > + m10v_xdmac_config_chan(mchan); > + > + m10v_xdmac_enable_chan(mchan); You dont check if anything is already running or not? > +static dma_cookie_t m10v_xdmac_tx_submit(struct dma_async_tx_descriptor *txd) > +{ > + struct m10v_dma_chan *mchan = to_m10v_dma_chan(txd->chan); > + dma_cookie_t cookie; > + unsigned long flags; > + > + spin_lock_irqsave(&mchan->lock, flags); > + cookie = dma_cookie_assign(txd); > + spin_unlock_irqrestore(&mchan->lock, flags); > + > + return cookie; sounds like vchan_tx_submit() i think you can use virt-dma layer and then get rid of artificial limit in driver and be able to queue up the txn on dmaengine. > +static struct dma_async_tx_descriptor * > +m10v_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, > + dma_addr_t src, size_t len, unsigned long flags) > +{ > + struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan); > + > + dma_async_tx_descriptor_init(&mchan->mdesc.txd, chan); > + mchan->mdesc.txd.tx_submit = m10v_xdmac_tx_submit; > + mchan->mdesc.txd.callback = NULL; > + mchan->mdesc.txd.flags = flags; > + mchan->mdesc.txd.cookie = -EBUSY; > + > + mchan->mdesc.len = len; > + mchan->mdesc.src = src; > + mchan->mdesc.dst = dst; > + > + return &mchan->mdesc.txd; So you support single descriptor and dont check if this has been already configured. So I guess this has been tested by doing txn one at a time and not submitted bunch of txn and wait for them to complete. Please fix that to really enable dmaengine capabilities. > +static int m10v_xdmac_remove(struct platform_device *pdev) > +{ > + struct m10v_dma_chan *mchan; > + struct m10v_dma_device *mdmac = platform_get_drvdata(pdev); > + int i; > + > + m10v_xdmac_disable_dma(mdmac); > + > + for (i = 0; i < mdmac->channels; i++) { > + mchan = &mdmac->mchan[i]; > + devm_free_irq(&pdev->dev, mchan->irq, mchan); > + } No call to dma_async_device_unregister()? -- ~Vinod