From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C852C43218 for ; Sun, 28 Apr 2019 00:26:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F42072077B for ; Sun, 28 Apr 2019 00:26:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="eMMIlShJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726344AbfD1A0D (ORCPT ); Sat, 27 Apr 2019 20:26:03 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:14541 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726119AbfD1A0C (ORCPT ); Sat, 27 Apr 2019 20:26:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556411162; x=1587947162; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+oUGHgJqcWHwoouX7Rm0bcEfYEaHBmJ/F/1Xg9NeC+A=; b=eMMIlShJFMZa/oUqvXwV7L6lEx1JwoPcsL+t65SxakLtzkdkPAz01XIK YO3opmv5D/F3uosm5yHgDHX5Ic3eqsl5xjBumrDT1RQFRCstxkzLBGq9v VLmo8fV+wFTgKPRm+wXiSInizGn8CH6SCPo6ns3aSQOJh5LHpuDT/JLxm TC1H8hJHlRigbBUHNUmNN0x40hrJxqTGVvKYS3Ankq5qHwbpVyVcCEJMd M5iH8/tb4BjxJUKeeMOa856b0kmxIKtjpk/F2WjIjMR7dl+3awvD9VdjY 7g9toUU8v0zYU+TN4U0/0kpWgGSDDM7G00qwqXI0XM6AZFcBtN3ASR4ua Q==; X-IronPort-AV: E=Sophos;i="5.60,403,1549900800"; d="scan'208";a="106993910" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 28 Apr 2019 08:26:02 +0800 IronPort-SDR: FxXD42aQXcam998uSeNMF182biq+/8dEOkZB9t99R7TafWmGt9f3Pa2UlII5Cw1O06MwjpMHXM /Nd/5tqJjl21TUMD328QHGkuaijeOvU/twWf/aN0NSepLyc5wjovkC2MnkbVyl3u959R2ZYKmn mLBWjcQHKNoXnS2Wzln6MACy1hrlhqHrzOojf2078KpT89fPH7S2YkLqrvwmOub9+lElxxF2aI Th4TBMHDZTLeOcm2pz3RmAn4y5msv/V2H445DHZtv48Js4eszzWU8JWqIlTvx3wvDb7nMVQyHq ShXRGpjLlcm6jadoL5TBMmUf Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 27 Apr 2019 17:04:36 -0700 IronPort-SDR: zKuZNCVXHVbSjmeYi7nZxcRThDHf0m26GzMjdNXhfgSLUb30lnMLtQz0/xWF+1BO5mIZ04MPOc uUCtIamZ7WrU5vykrnuS634CxUzyJlEt0qNwDNZNGwsJ5mKmnE0u40uhGsBz4ozIccpZx0ANC0 Z9U8Tq7pVLGKTvz6jjhQFCIwC1go4pk9jctwlc9LmuovOv93riPIy1mp7X2oSCk+z7u70eJ7Ij Du31JaKTwgSIkIJpv9jbOoSmpdmmTe2BpFa4Cy3QvuA64TlAB3QgGMWkXPfmDahsMEVBYcyR4m Gz0= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 27 Apr 2019 17:26:02 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Andreas Schwab , Anup Patel , Ard Biesheuvel , Catalin Marinas , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Sudeep Holla , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [RFT PATCH v4 0/5] Unify CPU topology across ARM & RISC-V Date: Sat, 27 Apr 2019 17:25:24 -0700 Message-Id: <20190428002529.14229-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cpu-map DT entry in ARM can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent its own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any significant functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. There was an opportunity to unify topology data structure for ARM32 done by patch 3/4. But, I refrained from making any other changes as I am not very well versed with original intention for some functions that are present in arch_topology.c. I hope this patch series can be served as a baseline for such changes in the future. The patches have been tested for RISC-V and compile tested for ARM64, ARM32 & x86. The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/qemu/tree/riscv_topology_dt HiFive Unleashed DT with topology node is available here. https://github.com/atishp04/opensbi/tree/HiFive_unleashed_topology It can be verified with OpenSBI with following additional compile time option. FW_PAYLOAD_FDT="unleashed_topology.dtb" Changes from v3->v4 1. Get rid of ARM32 specific information in topology strucuture. 2. Remove redundant functions from ARM32 and use common code instead. Changes from v2->v3 1. Cover letter update with experiment DT for topology changes. 2. Added the patch for [2]. Changes from v1->v2 1. ARM32 can now use the common code as well. Atish Patra (4): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. arm: Use common cpu_topology structure and functions. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../topology.txt => cpu/cpu-topology.txt} | 134 ++++++-- arch/arm/include/asm/topology.h | 20 -- arch/arm/kernel/topology.c | 60 +--- arch/arm64/include/asm/topology.h | 23 -- arch/arm64/kernel/topology.c | 303 +----------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/arch_topology.c | 300 ++++++++++++++++- drivers/base/topology.c | 1 + include/linux/arch_topology.h | 26 ++ 10 files changed, 445 insertions(+), 426 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Atish Patra Subject: [RFT PATCH v4 0/5] Unify CPU topology across ARM & RISC-V Date: Sat, 27 Apr 2019 17:25:24 -0700 Message-ID: <20190428002529.14229-1-atish.patra@wdc.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: Sender: linux-kernel-owner@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Andreas Schwab , Anup Patel , Ard Biesheuvel , Catalin Marinas , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Sudeep Holla List-Id: devicetree@vger.kernel.org The cpu-map DT entry in ARM can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent its own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any significant functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. There was an opportunity to unify topology data structure for ARM32 done by patch 3/4. But, I refrained from making any other changes as I am not very well versed with original intention for some functions that are present in arch_topology.c. I hope this patch series can be served as a baseline for such changes in the future. The patches have been tested for RISC-V and compile tested for ARM64, ARM32 & x86. The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/qemu/tree/riscv_topology_dt HiFive Unleashed DT with topology node is available here. https://github.com/atishp04/opensbi/tree/HiFive_unleashed_topology It can be verified with OpenSBI with following additional compile time option. FW_PAYLOAD_FDT="unleashed_topology.dtb" Changes from v3->v4 1. Get rid of ARM32 specific information in topology strucuture. 2. Remove redundant functions from ARM32 and use common code instead. Changes from v2->v3 1. Cover letter update with experiment DT for topology changes. 2. Added the patch for [2]. Changes from v1->v2 1. ARM32 can now use the common code as well. Atish Patra (4): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. arm: Use common cpu_topology structure and functions. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../topology.txt => cpu/cpu-topology.txt} | 134 ++++++-- arch/arm/include/asm/topology.h | 20 -- arch/arm/kernel/topology.c | 60 +--- arch/arm64/include/asm/topology.h | 23 -- arch/arm64/kernel/topology.c | 303 +----------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/arch_topology.c | 300 ++++++++++++++++- drivers/base/topology.c | 1 + include/linux/arch_topology.h | 26 ++ 10 files changed, 445 insertions(+), 426 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E8AFC43219 for ; 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27 Apr 2019 17:02:27 -0700 IronPort-SDR: zKuZNCVXHVbSjmeYi7nZxcRThDHf0m26GzMjdNXhfgSLUb30lnMLtQz0/xWF+1BO5mIZ04MPOc uUCtIamZ7WrU5vykrnuS634CxUzyJlEt0qNwDNZNGwsJ5mKmnE0u40uhGsBz4ozIccpZx0ANC0 Z9U8Tq7pVLGKTvz6jjhQFCIwC1go4pk9jctwlc9LmuovOv93riPIy1mp7X2oSCk+z7u70eJ7Ij Du31JaKTwgSIkIJpv9jbOoSmpdmmTe2BpFa4Cy3QvuA64TlAB3QgGMWkXPfmDahsMEVBYcyR4m Gz0= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 27 Apr 2019 17:26:02 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT PATCH v4 0/5] Unify CPU topology across ARM & RISC-V Date: Sat, 27 Apr 2019 17:25:24 -0700 Message-Id: <20190428002529.14229-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190427_172605_902856_4A66B28A X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Sudeep Holla , Rob Herring , Paul Walmsley , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Otto Sabart , Andreas Schwab Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org The cpu-map DT entry in ARM can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent its own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any significant functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. There was an opportunity to unify topology data structure for ARM32 done by patch 3/4. But, I refrained from making any other changes as I am not very well versed with original intention for some functions that are present in arch_topology.c. I hope this patch series can be served as a baseline for such changes in the future. The patches have been tested for RISC-V and compile tested for ARM64, ARM32 & x86. The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/qemu/tree/riscv_topology_dt HiFive Unleashed DT with topology node is available here. https://github.com/atishp04/opensbi/tree/HiFive_unleashed_topology It can be verified with OpenSBI with following additional compile time option. FW_PAYLOAD_FDT="unleashed_topology.dtb" Changes from v3->v4 1. Get rid of ARM32 specific information in topology strucuture. 2. Remove redundant functions from ARM32 and use common code instead. Changes from v2->v3 1. Cover letter update with experiment DT for topology changes. 2. Added the patch for [2]. Changes from v1->v2 1. ARM32 can now use the common code as well. Atish Patra (4): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. arm: Use common cpu_topology structure and functions. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../topology.txt => cpu/cpu-topology.txt} | 134 ++++++-- arch/arm/include/asm/topology.h | 20 -- arch/arm/kernel/topology.c | 60 +--- arch/arm64/include/asm/topology.h | 23 -- arch/arm64/kernel/topology.c | 303 +----------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/arch_topology.c | 300 ++++++++++++++++- drivers/base/topology.c | 1 + include/linux/arch_topology.h | 26 ++ 10 files changed, 445 insertions(+), 426 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) -- 2.21.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DE34C43218 for ; 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27 Apr 2019 17:02:27 -0700 IronPort-SDR: zKuZNCVXHVbSjmeYi7nZxcRThDHf0m26GzMjdNXhfgSLUb30lnMLtQz0/xWF+1BO5mIZ04MPOc uUCtIamZ7WrU5vykrnuS634CxUzyJlEt0qNwDNZNGwsJ5mKmnE0u40uhGsBz4ozIccpZx0ANC0 Z9U8Tq7pVLGKTvz6jjhQFCIwC1go4pk9jctwlc9LmuovOv93riPIy1mp7X2oSCk+z7u70eJ7Ij Du31JaKTwgSIkIJpv9jbOoSmpdmmTe2BpFa4Cy3QvuA64TlAB3QgGMWkXPfmDahsMEVBYcyR4m Gz0= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 27 Apr 2019 17:26:02 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT PATCH v4 0/5] Unify CPU topology across ARM & RISC-V Date: Sat, 27 Apr 2019 17:25:24 -0700 Message-Id: <20190428002529.14229-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190427_172605_902856_4A66B28A X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Sudeep Holla , Rob Herring , Paul Walmsley , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Otto Sabart , Andreas Schwab Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org The cpu-map DT entry in ARM can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent its own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any significant functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. There was an opportunity to unify topology data structure for ARM32 done by patch 3/4. But, I refrained from making any other changes as I am not very well versed with original intention for some functions that are present in arch_topology.c. I hope this patch series can be served as a baseline for such changes in the future. The patches have been tested for RISC-V and compile tested for ARM64, ARM32 & x86. The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/qemu/tree/riscv_topology_dt HiFive Unleashed DT with topology node is available here. https://github.com/atishp04/opensbi/tree/HiFive_unleashed_topology It can be verified with OpenSBI with following additional compile time option. FW_PAYLOAD_FDT="unleashed_topology.dtb" Changes from v3->v4 1. Get rid of ARM32 specific information in topology strucuture. 2. Remove redundant functions from ARM32 and use common code instead. Changes from v2->v3 1. Cover letter update with experiment DT for topology changes. 2. Added the patch for [2]. Changes from v1->v2 1. ARM32 can now use the common code as well. Atish Patra (4): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. arm: Use common cpu_topology structure and functions. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../topology.txt => cpu/cpu-topology.txt} | 134 ++++++-- arch/arm/include/asm/topology.h | 20 -- arch/arm/kernel/topology.c | 60 +--- arch/arm64/include/asm/topology.h | 23 -- arch/arm64/kernel/topology.c | 303 +----------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/arch_topology.c | 300 ++++++++++++++++- drivers/base/topology.c | 1 + include/linux/arch_topology.h | 26 ++ 10 files changed, 445 insertions(+), 426 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel