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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id s202sm2479151oih.42.2019.04.29.15.53.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Apr 2019 15:53:16 -0700 (PDT) Date: Mon, 29 Apr 2019 17:53:15 -0500 From: Rob Herring To: Stu Hsieh Cc: Mauro Carvalho Chehab , CK Hu , Mark Rutland , Matthias Brugger , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com Subject: Re: [PATCH v2 01/15] dt-bindings: media: Add binding for MT2712 MIPI-CSI2 Message-ID: <20190429225315.GA23589@bogus> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 16, 2019 at 05:30:01PM +0800, Stu Hsieh wrote: > Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC > > Signed-off-by: Stu Hsieh > --- > .../bindings/media/mediatek-mipicsi-camsv.txt | 53 ++++++++++++++++++ > .../media/mediatek-mipicsi-common.txt | 19 +++++++ > .../bindings/media/mediatek-mipicsi.txt | 54 +++++++++++++++++++ > 3 files changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > new file mode 100644 > index 000000000000..5f34974f12ac > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > @@ -0,0 +1,53 @@ > +* Mediatek MIPI-CSI2 receiver camsv > + > +Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs > + > +Required properties: > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. Looks like 2 regions in the example. What are they? > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 1 clock? > +- interrupts : interrupt number to the interrupt controller. > + > +Example: > + seninf1_mux_camsv0: seninf_mux_camsv@15002100 { > + reg = <0 0x15002120 0 0x40>, > + <0 0x15004000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf2_mux_camsv1: seninf_mux_camsv@15002500 { > + reg = <0 0x15002520 0 0x40>, > + <0 0x15005000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf3_mux_camsv2: seninf_mux_camsv@15002900 { > + reg = <0 0x15002920 0 0x40>, > + <0 0x15006000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf4_mux_camsv3: seninf_mux_camsv@15002D00 { > + reg = <0 0x15002D20 0 0x40>, > + <0 0x15007000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf5_mux_camsv4: seninf_mux_camsv@15003100 { > + reg = <0 0x15003120 0 0x40>, > + <0 0x15008000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + }; > + > + seninf6_mux_camsv5: seninf_mux_camsv@15003500 { > + reg = <0 0x15003520 0 0x40>, > + <0 0x15009000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > new file mode 100644 > index 000000000000..a67c744b75f0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > @@ -0,0 +1,19 @@ > +* Mediatek MIPI-CSI2 receiver common > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi-common" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. How many clocks and what are they? > + > + > +Example: > + mipicsi: mipicsi@15002000 { > + compatible = "mediatek,mt2712-mipicsi-common", "syscon"; > + reg = <0 0x15002000 0 0x10>; > + clocks = <&imgsys CLK_IMG_SENINF_CAM_EN>, > + <&imgsys CLK_IMG_SENINF_SCAM_EN>; > + }; > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > new file mode 100644 > index 000000000000..24741ed62b25 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > @@ -0,0 +1,54 @@ > +* Mediatek MIPI-CSI2 receiver > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. How many regions? > +- power-domains: a phandle to the power domain, see > + Documentation/devicetree/bindings/power/power_domain.txt for details. > +- mediatek,larb: must contain the local arbiters in the current Socs, see > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > + for details. > +- iommus: should point to the respective IOMMU block with master port as > + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > + for details. How many? > +- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the mipicsi port s/_/-/ How many entries? > +- mediatek,mipicsiid: the id of the mipicsi port What is this for? We generally don't do device indexes in DT. > +- mediatek,mipicsi: the common component of the two mipicsi port > + > +Example: > + mipicsi0: mipicsi@10217000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA0>, > + <&iommu0 M4U_PORT_CAM_DMA1>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + > + mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0 > + &seninf2_mux_camsv1 > + &seninf3_mux_camsv2 > + &seninf4_mux_camsv3>; > + reg = <0 0x10217000 0 0x60>, > + <0 0x15002100 0 0x4>, > + <0 0x15002300 0 0x100>; > + mediatek,mipicsiid = <0>; > + status="disabled"; Don't show status in examples. > + }; > + > + mipicsi1: mipicsi@10218000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA2>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + mediatek,seninf_mux_camsv = <&seninf5_mux_camsv4 > + &seninf6_mux_camsv5>; > + reg = <0 0x10218000 0 0x60>, > + <0 0x15002500 0 0x4>, > + <0 0x15002700 0 0x100>; > + mediatek,mipicsiid = <1>; > + status="disabled"; > + }; > \ No newline at end of file Fix this. > -- > 2.18.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v2 01/15] dt-bindings: media: Add binding for MT2712 MIPI-CSI2 Date: Mon, 29 Apr 2019 17:53:15 -0500 Message-ID: <20190429225315.GA23589@bogus> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Stu Hsieh Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Matthias Brugger , linux-mediatek@lists.infradead.org, CK Hu , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org List-Id: devicetree@vger.kernel.org On Tue, Apr 16, 2019 at 05:30:01PM +0800, Stu Hsieh wrote: > Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC > > Signed-off-by: Stu Hsieh > --- > .../bindings/media/mediatek-mipicsi-camsv.txt | 53 ++++++++++++++++++ > .../media/mediatek-mipicsi-common.txt | 19 +++++++ > .../bindings/media/mediatek-mipicsi.txt | 54 +++++++++++++++++++ > 3 files changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > new file mode 100644 > index 000000000000..5f34974f12ac > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > @@ -0,0 +1,53 @@ > +* Mediatek MIPI-CSI2 receiver camsv > + > +Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs > + > +Required properties: > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. Looks like 2 regions in the example. What are they? > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 1 clock? > +- interrupts : interrupt number to the interrupt controller. > + > +Example: > + seninf1_mux_camsv0: seninf_mux_camsv@15002100 { > + reg = <0 0x15002120 0 0x40>, > + <0 0x15004000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf2_mux_camsv1: seninf_mux_camsv@15002500 { > + reg = <0 0x15002520 0 0x40>, > + <0 0x15005000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf3_mux_camsv2: seninf_mux_camsv@15002900 { > + reg = <0 0x15002920 0 0x40>, > + <0 0x15006000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf4_mux_camsv3: seninf_mux_camsv@15002D00 { > + reg = <0 0x15002D20 0 0x40>, > + <0 0x15007000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf5_mux_camsv4: seninf_mux_camsv@15003100 { > + reg = <0 0x15003120 0 0x40>, > + <0 0x15008000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + }; > + > + seninf6_mux_camsv5: seninf_mux_camsv@15003500 { > + reg = <0 0x15003520 0 0x40>, > + <0 0x15009000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > new file mode 100644 > index 000000000000..a67c744b75f0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > @@ -0,0 +1,19 @@ > +* Mediatek MIPI-CSI2 receiver common > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi-common" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. How many clocks and what are they? > + > + > +Example: > + mipicsi: mipicsi@15002000 { > + compatible = "mediatek,mt2712-mipicsi-common", "syscon"; > + reg = <0 0x15002000 0 0x10>; > + clocks = <&imgsys CLK_IMG_SENINF_CAM_EN>, > + <&imgsys CLK_IMG_SENINF_SCAM_EN>; > + }; > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > new file mode 100644 > index 000000000000..24741ed62b25 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > @@ -0,0 +1,54 @@ > +* Mediatek MIPI-CSI2 receiver > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. How many regions? > +- power-domains: a phandle to the power domain, see > + Documentation/devicetree/bindings/power/power_domain.txt for details. > +- mediatek,larb: must contain the local arbiters in the current Socs, see > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > + for details. > +- iommus: should point to the respective IOMMU block with master port as > + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > + for details. How many? > +- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the mipicsi port s/_/-/ How many entries? > +- mediatek,mipicsiid: the id of the mipicsi port What is this for? We generally don't do device indexes in DT. > +- mediatek,mipicsi: the common component of the two mipicsi port > + > +Example: > + mipicsi0: mipicsi@10217000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA0>, > + <&iommu0 M4U_PORT_CAM_DMA1>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + > + mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0 > + &seninf2_mux_camsv1 > + &seninf3_mux_camsv2 > + &seninf4_mux_camsv3>; > + reg = <0 0x10217000 0 0x60>, > + <0 0x15002100 0 0x4>, > + <0 0x15002300 0 0x100>; > + mediatek,mipicsiid = <0>; > + status="disabled"; Don't show status in examples. > + }; > + > + mipicsi1: mipicsi@10218000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA2>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + mediatek,seninf_mux_camsv = <&seninf5_mux_camsv4 > + &seninf6_mux_camsv5>; > + reg = <0 0x10218000 0 0x60>, > + <0 0x15002500 0 0x4>, > + <0 0x15002700 0 0x100>; > + mediatek,mipicsiid = <1>; > + status="disabled"; > + }; > \ No newline at end of file Fix this. > -- > 2.18.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A770C43219 for ; Mon, 29 Apr 2019 22:53:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 691B62075E for ; Mon, 29 Apr 2019 22:53:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uTapcT5z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 691B62075E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zrM/IPxKjVkUhdwHwmR40jgtBJCMfbVEGPHSJPmODeE=; b=uTapcT5zn7poOS B6PGvYKIp7cLQKBykNCc+i39FIdjePI97xmC0wY51fFA8cdNtH/GF61h4pWYGnUrPccmeXTF5s+Z6 dtjDyw67kYaocFkVSPIM4tFZqKGOWzCaH6NBaacKUQoF4pWDngCZV8h1VIzvY2SQdGVV8w8qInlGS OBt2ch/cVqaytHiFZdvCj8bAbWnP1msng/Kl8IwgLTIsE5BoO9c+iqIvVVlCmT4UqWytG6yi2S6Wx G10nyv1ubu2lT6xkcnBj8JCfPCpojfQV3Dl0v0CGCKeTa7Bnb1eArf+FHTX9pF5ZzviwBqaxbRmlR f4npXdyck2bDOmkVdphQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLF9G-0005ll-OL; Mon, 29 Apr 2019 22:53:22 +0000 Received: from mail-ot1-f68.google.com ([209.85.210.68]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLF9C-0005lB-Pi; Mon, 29 Apr 2019 22:53:21 +0000 Received: by mail-ot1-f68.google.com with SMTP id s11so5905604otp.0; Mon, 29 Apr 2019 15:53:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=TJyEVrvktv6Tufpho/NZ7KCvbKlhL+8KY18oT1f7uHk=; b=hsSO+xW+GlOkfjbN614Hl4hAmwckMqs5P/pfLSmZAu/zFEtsSQrLKZKEs+s6xPEyOD PnRqEQVKc4pcHTzn+KRDcH1hsPnEoA5wdWs35qdL4YQkr8fwiyVQl57TVpEioXA3tgw5 0mr4ky39xJOSRfE98qhVi53ImMVBno2Hl3+vPdwy5JhZfjU/xxHrcQBEpOECx4a45mSS 2qjXfXRjNdqXpRjB9XgfICAWs7LOwNqST1z0ZR+gvzV1T8kgmj5Xc+eQaaGc55Jz+eeQ jKk0rqNwa2D7/iEXYdZcDtVtZ3T5cU1h8w2i1ByWpLJOUgaIx1++Ixk8C9VIPJcZxwAI iiww== X-Gm-Message-State: APjAAAV1SqRpSJID///UqdJgtvbLL4rtQtsHDfFgVQKdxtgxxfjc4P19 OZWYL0e0STvR/O0hwvO51g== X-Google-Smtp-Source: APXvYqxyLs6MFB7n9d1LRFWLjpK15UJ0Vz05okp6i1ecyTDNMHsqOeG5GSjwhhfcQTOtr1suT8/yeg== X-Received: by 2002:a05:6830:4d:: with SMTP id d13mr8171393otp.106.1556578397797; Mon, 29 Apr 2019 15:53:17 -0700 (PDT) Received: from localhost (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id s202sm2479151oih.42.2019.04.29.15.53.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Apr 2019 15:53:16 -0700 (PDT) Date: Mon, 29 Apr 2019 17:53:15 -0500 From: Rob Herring To: Stu Hsieh Subject: Re: [PATCH v2 01/15] dt-bindings: media: Add binding for MT2712 MIPI-CSI2 Message-ID: <20190429225315.GA23589@bogus> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190429_155318_831452_E04961EB X-CRM114-Status: GOOD ( 19.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Matthias Brugger , linux-mediatek@lists.infradead.org, CK Hu , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 16, 2019 at 05:30:01PM +0800, Stu Hsieh wrote: > Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC > > Signed-off-by: Stu Hsieh > --- > .../bindings/media/mediatek-mipicsi-camsv.txt | 53 ++++++++++++++++++ > .../media/mediatek-mipicsi-common.txt | 19 +++++++ > .../bindings/media/mediatek-mipicsi.txt | 54 +++++++++++++++++++ > 3 files changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > new file mode 100644 > index 000000000000..5f34974f12ac > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt > @@ -0,0 +1,53 @@ > +* Mediatek MIPI-CSI2 receiver camsv > + > +Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs > + > +Required properties: > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. Looks like 2 regions in the example. What are they? > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 1 clock? > +- interrupts : interrupt number to the interrupt controller. > + > +Example: > + seninf1_mux_camsv0: seninf_mux_camsv@15002100 { > + reg = <0 0x15002120 0 0x40>, > + <0 0x15004000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf2_mux_camsv1: seninf_mux_camsv@15002500 { > + reg = <0 0x15002520 0 0x40>, > + <0 0x15005000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; > + interrupts = ; > + }; > + > + seninf3_mux_camsv2: seninf_mux_camsv@15002900 { > + reg = <0 0x15002920 0 0x40>, > + <0 0x15006000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf4_mux_camsv3: seninf_mux_camsv@15002D00 { > + reg = <0 0x15002D20 0 0x40>, > + <0 0x15007000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; > + interrupts = ; > + }; > + > + seninf5_mux_camsv4: seninf_mux_camsv@15003100 { > + reg = <0 0x15003120 0 0x40>, > + <0 0x15008000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + }; > + > + seninf6_mux_camsv5: seninf_mux_camsv@15003500 { > + reg = <0 0x15003520 0 0x40>, > + <0 0x15009000 0 0x1000>; > + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; > + interrupts = ; > + > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > new file mode 100644 > index 000000000000..a67c744b75f0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt > @@ -0,0 +1,19 @@ > +* Mediatek MIPI-CSI2 receiver common > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi-common" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. > +- clocks: device clocks, see > + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. How many clocks and what are they? > + > + > +Example: > + mipicsi: mipicsi@15002000 { > + compatible = "mediatek,mt2712-mipicsi-common", "syscon"; > + reg = <0 0x15002000 0 0x10>; > + clocks = <&imgsys CLK_IMG_SENINF_CAM_EN>, > + <&imgsys CLK_IMG_SENINF_SCAM_EN>; > + }; > diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > new file mode 100644 > index 000000000000..24741ed62b25 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt > @@ -0,0 +1,54 @@ > +* Mediatek MIPI-CSI2 receiver > + > +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs > + > +Required properties: > +- compatible: should be "mediatek,mt2712-mipicsi" > +- reg : physical base address of the mipicsi receiver registers and length of > + memory mapped region. How many regions? > +- power-domains: a phandle to the power domain, see > + Documentation/devicetree/bindings/power/power_domain.txt for details. > +- mediatek,larb: must contain the local arbiters in the current Socs, see > + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > + for details. > +- iommus: should point to the respective IOMMU block with master port as > + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > + for details. How many? > +- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the mipicsi port s/_/-/ How many entries? > +- mediatek,mipicsiid: the id of the mipicsi port What is this for? We generally don't do device indexes in DT. > +- mediatek,mipicsi: the common component of the two mipicsi port > + > +Example: > + mipicsi0: mipicsi@10217000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA0>, > + <&iommu0 M4U_PORT_CAM_DMA1>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + > + mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0 > + &seninf2_mux_camsv1 > + &seninf3_mux_camsv2 > + &seninf4_mux_camsv3>; > + reg = <0 0x10217000 0 0x60>, > + <0 0x15002100 0 0x4>, > + <0 0x15002300 0 0x100>; > + mediatek,mipicsiid = <0>; > + status="disabled"; Don't show status in examples. > + }; > + > + mipicsi1: mipicsi@10218000 { > + compatible = "mediatek,mt2712-mipicsi"; > + mediatek,mipicsi = <&mipicsi>; > + iommus = <&iommu0 M4U_PORT_CAM_DMA2>; > + mediatek,larb = <&larb2>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; > + mediatek,seninf_mux_camsv = <&seninf5_mux_camsv4 > + &seninf6_mux_camsv5>; > + reg = <0 0x10218000 0 0x60>, > + <0 0x15002500 0 0x4>, > + <0 0x15002700 0 0x100>; > + mediatek,mipicsiid = <1>; > + status="disabled"; > + }; > \ No newline at end of file Fix this. > -- > 2.18.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel