From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Chris Brandt Subject: [PATCH 6/7] ARM: dts: r7s9210-rza2mevb: Add Ethernet support Date: Tue, 30 Apr 2019 08:23:08 -0500 Message-ID: <20190430132309.12473-7-chris.brandt@renesas.com> In-Reply-To: <20190430132309.12473-1-chris.brandt@renesas.com> References: <20190430132309.12473-1-chris.brandt@renesas.com> MIME-Version: 1.0 Content-Type: text/plain To: Simon Horman , Rob Herring , Mark Cc: devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt List-ID: The RZ/A2M EVB sub board has 2 Ethernet jacks on it. Set switch SW6_4 to ON to use Ethernet Ch-0 Set switch SW6_5 to ON to use Ethernet Ch-1 Signed-off-by: Chris Brandt --- arch/arm/boot/dts/r7s9210-rza2mevb.dts | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 42005acb848c..df69746244fe 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -62,6 +62,34 @@ pinmux = , /* TxD4 */ ; /* RxD4 */ }; + + eth0_pins: eth0 { + pinmux = , /* REF50CK0 */ + , /* RMMI0_TXDEN */ + , /* RMII0_TXD0 */ + , /* RMII0_TXD1 */ + , /* RMII0_CRSDV */ + , /* RMII0_RXD0 */ + , /* RMII0_RXD1 */ + , /* RMII0_RXER */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* IRQ4 */ + }; + + eth1_pins: eth1 { + pinmux = , /* REF50CK1 */ + , /* RMMI1_TXDEN */ + , /* RMII1_TXD0 */ + , /* RMII1_TXD1 */ + , /* RMII1_CRSDV */ + , /* RMII1_RXD0 */ + , /* RMII1_RXD1 */ + , /* RMII1_RXER */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* IRQ5 */ + }; }; /* High resolution System tick timers */ @@ -80,3 +108,25 @@ status = "okay"; }; + +ðer0 { + pinctrl-names = "default"; + pinctrl-0 = <ð0_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ðer1 { + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <0>; + }; +}; -- 2.16.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D24DC43219 for ; Tue, 30 Apr 2019 13:33:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6611220644 for ; Tue, 30 Apr 2019 13:33:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726679AbfD3Ndc (ORCPT ); Tue, 30 Apr 2019 09:33:32 -0400 Received: from pbmsgap02.intersil.com ([192.157.179.202]:40568 "EHLO pbmsgap02.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbfD3Ndc (ORCPT ); Tue, 30 Apr 2019 09:33:32 -0400 Received: from pps.filterd (pbmsgap02.intersil.com [127.0.0.1]) by pbmsgap02.intersil.com (8.16.0.27/8.16.0.27) with SMTP id x3UDNK9G032150; Tue, 30 Apr 2019 09:23:27 -0400 Received: from pbmxdp02.intersil.corp (pbmxdp02.pb.intersil.com [132.158.200.223]) by pbmsgap02.intersil.com with ESMTP id 2s4h8d2csk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 30 Apr 2019 09:23:26 -0400 Received: from pbmxdp03.intersil.corp (132.158.200.224) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Tue, 30 Apr 2019 09:23:25 -0400 Received: from localhost.localdomain (132.158.202.108) by pbmxdp03.intersil.corp (132.158.200.224) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Tue, 30 Apr 2019 09:23:25 -0400 From: Chris Brandt To: Simon Horman , Rob Herring , "Mark Rutland" CC: , , , Chris Brandt Subject: [PATCH 6/7] ARM: dts: r7s9210-rza2mevb: Add Ethernet support Date: Tue, 30 Apr 2019 08:23:08 -0500 Message-ID: <20190430132309.12473-7-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20190430132309.12473-1-chris.brandt@renesas.com> References: <20190430132309.12473-1-chris.brandt@renesas.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-30_06:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=727 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1904300086 X-Proofpoint-Spam-Reason: mlx Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RZ/A2M EVB sub board has 2 Ethernet jacks on it. Set switch SW6_4 to ON to use Ethernet Ch-0 Set switch SW6_5 to ON to use Ethernet Ch-1 Signed-off-by: Chris Brandt --- arch/arm/boot/dts/r7s9210-rza2mevb.dts | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 42005acb848c..df69746244fe 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -62,6 +62,34 @@ pinmux = , /* TxD4 */ ; /* RxD4 */ }; + + eth0_pins: eth0 { + pinmux = , /* REF50CK0 */ + , /* RMMI0_TXDEN */ + , /* RMII0_TXD0 */ + , /* RMII0_TXD1 */ + , /* RMII0_CRSDV */ + , /* RMII0_RXD0 */ + , /* RMII0_RXD1 */ + , /* RMII0_RXER */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* IRQ4 */ + }; + + eth1_pins: eth1 { + pinmux = , /* REF50CK1 */ + , /* RMMI1_TXDEN */ + , /* RMII1_TXD0 */ + , /* RMII1_TXD1 */ + , /* RMII1_CRSDV */ + , /* RMII1_RXD0 */ + , /* RMII1_RXD1 */ + , /* RMII1_RXER */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* IRQ5 */ + }; }; /* High resolution System tick timers */ @@ -80,3 +108,25 @@ status = "okay"; }; + +ðer0 { + pinctrl-names = "default"; + pinctrl-0 = <ð0_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ðer1 { + pinctrl-names = "default"; + pinctrl-0 = <ð1_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <0>; + }; +}; -- 2.16.1