From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Subject: Re: [PATCH v3 3/3] PCI: qcom: Add QCS404 PCIe controller support Date: Thu, 2 May 2019 17:29:37 +0530 Message-ID: <20190502115937.GO3845@vkoul-mobl.Dlink> References: <20190502001955.10575-1-bjorn.andersson@linaro.org> <20190502001955.10575-4-bjorn.andersson@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190502001955.10575-4-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Bjorn Andersson Cc: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On 01-05-19, 17:19, Bjorn Andersson wrote: > The QCS404 platform contains a PCIe controller of version 2.4.0 and a > Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the > IPQ4019, but this support touches clocks and resets related to the PHY > as well, and there's no upstream driver for the PHY. > > On QCS404 we must initialize the PHY, so a separate PHY driver is > implemented to take care of this and the controller driver is updated to > not require the PHY related resources. This is done by relying on the > fact that operations in both the clock and reset framework are nops when > passed NULL, so we can isolate this change to only the get_resource > function. > > For QCS404 we also need to enable the AHB (iface) clock, in order to > access the register space of the controller, but as this is not part of > the IPQ4019 DT binding this is only added for new users of the 2.4.0 > controller. Reviewed-by: Vinod Koul -- ~Vinod