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From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 11/18] x86: Fix device-tree indentation
Date: Thu,  2 May 2019 10:52:21 -0600	[thread overview]
Message-ID: <20190502165229.203099-12-sjg@chromium.org> (raw)
In-Reply-To: <20190502165229.203099-1-sjg@chromium.org>

With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 147 +++++++++++++++++++--------------------
 1 file changed, 73 insertions(+), 74 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 6b176339aed..daeb168b65f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -23,42 +23,41 @@
 
 #ifdef CONFIG_ROM_SIZE
 &rom {
-		filename = "u-boot.rom";
-		end-at-4gb;
-		sort-by-offset;
-		pad-byte = <0xff>;
-		size = <CONFIG_ROM_SIZE>;
+	filename = "u-boot.rom";
+	end-at-4gb;
+	sort-by-offset;
+	pad-byte = <0xff>;
+	size = <CONFIG_ROM_SIZE>;
 #ifdef CONFIG_HAVE_INTEL_ME
-		intel-descriptor {
-			filename = CONFIG_FLASH_DESCRIPTOR_FILE;
-		};
-		intel-me {
-			filename = CONFIG_INTEL_ME_FILE;
-		};
+	intel-descriptor {
+		filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+	};
+	intel-me {
+		filename = CONFIG_INTEL_ME_FILE;
+	};
 #endif
 #ifdef CONFIG_TPL
-		u-boot-tpl-with-ucode-ptr {
-			offset = <CONFIG_TPL_TEXT_BASE>;
-		};
-		u-boot-tpl-dtb {
-		};
-		u-boot-spl {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-		u-boot-spl-dtb {
-		};
-		u-boot {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-tpl-with-ucode-ptr {
+		offset = <CONFIG_TPL_TEXT_BASE>;
+	};
+	u-boot-tpl-dtb {
+	};
+	u-boot-spl {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-spl-dtb {
+	};
+	u-boot {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #elif defined(CONFIG_SPL)
-		u-boot-spl-with-ucode-ptr {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-
-		u-boot-dtb-with-ucode2 {
-			type = "u-boot-dtb-with-ucode";
-		};
-		u-boot {
+	u-boot-spl-with-ucode-ptr {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-dtb-with-ucode2 {
+		type = "u-boot-dtb-with-ucode";
+	};
+	u-boot {
 		/*
 		 * TODO(sjg at chromium.org):
 		 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
@@ -68,67 +67,67 @@
 		 * We need a better solution, perhaps a separate Kconfig.
 		 */
 #if CONFIG_SYS_TEXT_BASE == 0x1110000
-			offset = <0xfff00000>;
+		offset = <0xfff00000>;
 #else
-			offset = <CONFIG_SYS_TEXT_BASE>;
+		offset = <CONFIG_SYS_TEXT_BASE>;
 #endif
-		};
+	};
 #else
-		u-boot-with-ucode-ptr {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-with-ucode-ptr {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #endif
-		u-boot-dtb-with-ucode {
-		};
-		u-boot-ucode {
-			align = <16>;
-		};
+	u-boot-dtb-with-ucode {
+	};
+	u-boot-ucode {
+		align = <16>;
+	};
 #ifdef CONFIG_HAVE_MRC
-		intel-mrc {
-			offset = <CONFIG_X86_MRC_ADDR>;
-		};
+	intel-mrc {
+		offset = <CONFIG_X86_MRC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_FSP
-		intel-fsp {
-			filename = CONFIG_FSP_FILE;
-			offset = <CONFIG_FSP_ADDR>;
-		};
+	intel-fsp {
+		filename = CONFIG_FSP_FILE;
+		offset = <CONFIG_FSP_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_CMC
-		intel-cmc {
-			filename = CONFIG_CMC_FILE;
-			offset = <CONFIG_CMC_ADDR>;
-		};
+	intel-cmc {
+		filename = CONFIG_CMC_FILE;
+		offset = <CONFIG_CMC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VGA_BIOS
-		intel-vga {
-			filename = CONFIG_VGA_BIOS_FILE;
-			offset = <CONFIG_VGA_BIOS_ADDR>;
-		};
+	intel-vga {
+		filename = CONFIG_VGA_BIOS_FILE;
+		offset = <CONFIG_VGA_BIOS_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VBT
-		intel-vbt {
-			filename = CONFIG_VBT_FILE;
-			offset = <CONFIG_VBT_ADDR>;
-		};
+	intel-vbt {
+		filename = CONFIG_VBT_FILE;
+		offset = <CONFIG_VBT_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_REFCODE
-		intel-refcode {
-			offset = <CONFIG_X86_REFCODE_ADDR>;
-		};
+	intel-refcode {
+		offset = <CONFIG_X86_REFCODE_ADDR>;
+	};
 #endif
 #ifdef CONFIG_TPL
-		x86-start16-tpl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-tpl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #elif defined(CONFIG_SPL)
-		x86-start16-spl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-spl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #else
-		x86-start16 {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16 {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #endif
 };
 #endif
-- 
2.21.0.1020.gf2820cf01a-goog

  parent reply	other threads:[~2019-05-02 16:52 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-02 16:52 [U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL Simon Glass
2019-05-02 16:52 ` [U-Boot] [PATCH v3 01/18] cros_ec: Use a hyphen in the uclass name Simon Glass
2019-05-07  9:10   ` Bin Meng
2019-05-07  9:21     ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 02/18] x86: Add a simple TPL implementation Simon Glass
2019-05-07  9:21   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 03/18] x86: sysreset: Separate out the EFI code Simon Glass
2019-05-07  9:21   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 04/18] x86: sysreset: Implement power-off if available Simon Glass
2019-05-07  9:21   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 05/18] x86: sysreset: Implement the get_last() method Simon Glass
2019-05-07  9:21   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 06/18] x86: Add documention on the samus flashmap Simon Glass
2019-05-07  9:21   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 07/18] x86: samus: Update device tree for SPL Simon Glass
2019-05-07  9:10   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 08/18] x86: samus: Update device tree for verified boot Simon Glass
2019-05-02 16:52 ` [U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL Simon Glass
2019-05-07  9:10   ` Bin Meng
2019-05-07  9:26     ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 10/18] x86: Update device tree for Chromium OS verified boot Simon Glass
2019-05-07  9:26   ` Bin Meng
2019-05-02 16:52 ` Simon Glass [this message]
2019-05-07  9:26   ` [U-Boot] [PATCH v3 11/18] x86: Fix device-tree indentation Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 12/18] x86: samus: Increase the pre-reloc memory again Simon Glass
2019-05-07  9:26   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 13/18] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" Simon Glass
2019-05-02 16:52 ` [U-Boot] [PATCH v3 14/18] x86: Enable the RTC on all boards Simon Glass
2019-05-07  9:10   ` Bin Meng
2019-05-07  9:31     ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 15/18] x86: Update the memory map a little Simon Glass
2019-05-07  9:31   ` Bin Meng
2019-05-07  9:46     ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 16/18] x86: broadwell: Update PCH to work in TPL Simon Glass
2019-05-07  9:31   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 17/18] x86: Add a way to jump from TPL to SPL Simon Glass
2019-05-07  9:31   ` Bin Meng
2019-05-02 16:52 ` [U-Boot] [PATCH v3 18/18] x86: samus: Add a target to boot through TPL Simon Glass
2019-05-07 10:07 ` [U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL Bin Meng
2019-05-08  3:33   ` Bin Meng
2019-05-08  3:41     ` Simon Glass
2019-05-08  4:52       ` Bin Meng

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