From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Thu, 2 May 2019 10:52:17 -0600 Subject: [U-Boot] [PATCH v3 07/18] x86: samus: Update device tree for SPL In-Reply-To: <20190502165229.203099-1-sjg@chromium.org> References: <20190502165229.203099-1-sjg@chromium.org> Message-ID: <20190502165229.203099-8-sjg@chromium.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add tags to allow required nodes to be present in SPL / TPL. Also enable the sysreset driver. Signed-off-by: Simon Glass --- Changes in v3: - Remove unneeded pch-reset node Changes in v2: None arch/x86/dts/chromebook_samus.dts | 33 +++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 35211ed81b1..33df0e1f718 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -17,6 +17,7 @@ spi0 = &spi; usb0 = &usb_0; usb1 = &usb_1; + cros-ec0 = &cros_ec; }; config { @@ -73,6 +74,7 @@ /* Put this first: it is the default */ gpio_unused: gpio-unused { + u-boot,dm-pre-reloc; mode-gpio; direction = ; owner = ; @@ -80,6 +82,7 @@ }; gpio_acpi_sci: acpi-sci { + u-boot,dm-pre-reloc; mode-gpio; direction = ; invert; @@ -87,6 +90,7 @@ }; gpio_acpi_smi: acpi-smi { + u-boot,dm-pre-reloc; mode-gpio; direction = ; invert; @@ -94,12 +98,14 @@ }; gpio_input: gpio-input { + u-boot,dm-pre-reloc; mode-gpio; direction = ; owner = ; }; gpio_input_invert: gpio-input-invert { + u-boot,dm-pre-reloc; mode-gpio; direction = ; owner = ; @@ -107,9 +113,11 @@ }; gpio_native: gpio-native { + u-boot,dm-pre-reloc; }; gpio_out_high: gpio-out-high { + u-boot,dm-pre-reloc; mode-gpio; direction = ; output-value = <1>; @@ -118,6 +126,7 @@ }; gpio_out_low: gpio-out-low { + u-boot,dm-pre-reloc; mode-gpio; direction = ; output-value = <0>; @@ -126,6 +135,7 @@ }; gpio_pirq: gpio-pirq { + u-boot,dm-pre-reloc; mode-gpio; direction = ; owner = ; @@ -133,6 +143,7 @@ }; soc_gpio at 0 { + u-boot,dm-pre-reloc; config = <0 &gpio_unused 0>, /* unused */ <1 &gpio_unused 0>, /* unused */ @@ -250,8 +261,10 @@ spd { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; samsung_4 { reg = <6>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 04 11 05 0b 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -291,6 +304,7 @@ * columns 10, density 4096 mb, x32 */ reg = <8>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 04 11 05 0b 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -326,6 +340,7 @@ }; samsung_8 { reg = <10>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 04 12 05 0a 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -365,6 +380,7 @@ * columns 11, density 4096 mb, x16 */ reg = <12>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 04 12 05 0a 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -404,6 +420,7 @@ * columns 11, density 8192 mb, x16 */ reg = <13>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 05 1a 05 0a 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -443,6 +460,7 @@ * columns 11, density 8192 mb, x16 */ reg = <15>; + u-boot,dm-pre-reloc; data = [91 20 f1 03 05 1a 05 0a 03 11 01 08 0a 00 50 01 78 78 90 50 90 11 50 e0 @@ -540,7 +558,7 @@ compatible = "ehci-pci"; }; - pch at 1f,0 { + pch: pch at 1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,broadwell-pch"; u-boot,dm-pre-reloc; @@ -559,17 +577,20 @@ power-enable-gpio = <&gpio_a 23 0>; spi: spi { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; spi-flash at 0 { + u-boot,dm-pre-reloc; #size-cells = <1>; #address-cells = <1>; reg = <0>; compatible = "winbond,w25q64", "jedec,spi-nor"; - memory-map = <0xff800000 0x00800000>; + memory-map = <0 0xff800000 0 0x00800000>; rw-mrc-cache { + u-boot,dm-pre-reloc; label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; }; @@ -609,7 +630,8 @@ #size-cells = <0>; u-boot,dm-pre-reloc; intel,gen-dec = <0x800 0xfc 0x900 0xfc>; - cros-ec at 200 { + cros_ec: cros-ec { + u-boot,dm-pre-reloc; compatible = "google,cros-ec-lpc"; reg = <0x204 1 0x200 1 0x880 0x80>; @@ -630,7 +652,7 @@ sata at 1f,2 { compatible = "intel,wildcatpoint-ahci"; reg = <0x0000fa00 0 0 0 0>; - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; intel,sata-mode = "ahci"; intel,sata-port-map = <1>; intel,sata-port0-gen3-tx = <0x72>; @@ -645,12 +667,15 @@ }; tpm { + u-boot,dm-pre-reloc; reg = <0xfed40000 0x5000>; compatible = "infineon,slb9635lpc"; }; microcode { + u-boot,dm-pre-reloc; update at 0 { + u-boot,dm-pre-reloc; #include "microcode/mc0306d4_00000018.dtsi" }; }; -- 2.21.0.1020.gf2820cf01a-goog