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* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
@ 2019-05-06 14:02 Niel Fourie
  2019-05-06 14:18 ` Tom Rini
  0 siblings, 1 reply; 9+ messages in thread
From: Niel Fourie @ 2019-05-06 14:02 UTC (permalink / raw)
  To: u-boot

Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM:  256 MiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet at 4a100000

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit 37624b58542f ("Linux 5.1-rc7")

Signed-off-by: Niel Fourie <lusus@denx.de>

---
Changes for v2:
- Remove formatting changes to upstream Linux dtsi files
- Remove incorrectly added MACH_TYPE
- Rename board from phycore_pcl060 to phycore_am335x_r2
- Implement selecting memory size from device tree
- Remove non-DM Ethernet board code
- General clean-up

Changes for v3:
- Added kernel revision of upstream Linux dtsi files
- Place TARGET_PHYCORE_AM335X_R2 alphabetically in Kconfig
- Rework TPS65910 I2C init code
- Remove non-DM USB board macros
- Minor tweaks

Changes for v4:
- Propose abstracting common sections to am33xx-u-boot.dtsi
- Remove dead Falcon mode code
- Remove non-DM I2C support for TPS65910 I2C

Changes for v5:
- Revert proposed moving of sections to am33xx-u-boot.dtsi
- Remove redundant/incorrect lines from am33xx-u-boot.dtsi
- Add missing changelog

 arch/arm/dts/Makefile                      |   3 +-
 arch/arm/dts/am335x-phycore-som.dtsi       | 322 +++++++++++++++++++++
 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi   |  31 ++
 arch/arm/dts/am335x-wega-rdk.dts           |  23 ++
 arch/arm/dts/am335x-wega.dtsi              | 230 +++++++++++++++
 arch/arm/mach-omap2/Kconfig                |   1 +
 arch/arm/mach-omap2/am33xx/Kconfig         |   7 +
 board/phytec/phycore_am335x_r2/Kconfig     |  15 +
 board/phytec/phycore_am335x_r2/MAINTAINERS |   7 +
 board/phytec/phycore_am335x_r2/Makefile    |  11 +
 board/phytec/phycore_am335x_r2/board.c     | 252 ++++++++++++++++
 board/phytec/phycore_am335x_r2/board.h     |  24 ++
 board/phytec/phycore_am335x_r2/mux.c       | 117 ++++++++
 configs/phycore-am335x-r2-wega_defconfig   |  79 +++++
 include/configs/phycore_am335x_r2.h        | 130 +++++++++
 15 files changed, 1251 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/am335x-phycore-som.dtsi
 create mode 100644 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/am335x-wega-rdk.dts
 create mode 100644 arch/arm/dts/am335x-wega.dtsi
 create mode 100644 board/phytec/phycore_am335x_r2/Kconfig
 create mode 100644 board/phytec/phycore_am335x_r2/MAINTAINERS
 create mode 100644 board/phytec/phycore_am335x_r2/Makefile
 create mode 100644 board/phytec/phycore_am335x_r2/board.c
 create mode 100644 board/phytec/phycore_am335x_r2/board.h
 create mode 100644 board/phytec/phycore_am335x_r2/mux.c
 create mode 100644 configs/phycore-am335x-r2-wega_defconfig
 create mode 100644 include/configs/phycore_am335x_r2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e082f2840..381a64ae13 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -264,7 +264,8 @@ dtb-$(CONFIG_AM33XX) += \
 	am335x-chiliboard.dtb \
 	am335x-sl50.dtb \
 	am335x-base0033.dtb \
-	am335x-guardian.dtb
+	am335x-guardian.dtb \
+	am335x-wega-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb \
diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi
new file mode 100644
index 0000000000..8d7c19e5e1
--- /dev/null
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Phytec AM335x phyCORE";
+	compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+	aliases {
+		rtc0 = &i2c_rtc;
+		rtc1 = &rtc;
+	};
+
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		vcc5v: fixedregulator0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc5v";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+/* Crypto Module */
+&aes {
+	status = "okay";
+};
+
+&sham {
+	status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+	ethernet0_pins: pinmux_ethernet0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)		/* mii1_txen.rmii1_txen */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+		>;
+	};
+
+	mdio_pins: pinmux_mdio {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+};
+
+&cpsw_emac0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+	status = "okay";
+
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+};
+
+&mac {
+	slaves = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet0_pins>;
+	status = "okay";
+};
+
+/* I2C Busses */
+&am33xx_pinmux {
+	i2c0_pins: pinmux_i2c0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	tps: pmic at 2d {
+		reg = <0x2d>;
+	};
+
+	i2c_tmp102: temp at 4b {
+		compatible = "ti,tmp102";
+		reg = <0x4b>;
+		status = "disabled";
+	};
+
+	i2c_eeprom: eeprom at 52 {
+		compatible = "atmel,24c32";
+		pagesize = <32>;
+		reg = <0x52>;
+		status = "disabled";
+	};
+
+	i2c_rtc: rtc at 68 {
+		compatible = "microcrystal,rv4162";
+		reg = <0x68>;
+		status = "disabled";
+	};
+};
+
+/* NAND memory */
+&am33xx_pinmux {
+		nandflash_pins: pinmux_nandflash {
+			pinctrl-single,pins = <
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
+			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins>;
+	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
+	nandflash: nand at 0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <30>;
+		gpmc,cs-wr-off-ns = <30>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <30>;
+		gpmc,adv-wr-off-ns = <30>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <20>;
+		gpmc,oe-on-ns = <10>;
+		gpmc,oe-off-ns = <30>;
+		gpmc,access-ns = <30>;
+		gpmc,rd-cycle-ns = <30>;
+		gpmc,wr-cycle-ns = <30>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <50>;
+		gpmc,cycle2cycle-diffcsen;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <30>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		ti,elm-id = <&elm>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+/* Power */
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vcc5v>;
+	vcc2-supply = <&vcc5v>;
+	vcc3-supply = <&vcc5v>;
+	vcc4-supply = <&vcc5v>;
+	vcc5-supply = <&vcc5v>;
+	vcc6-supply = <&vcc5v>;
+	vcc7-supply = <&vcc5v>;
+	vccio-supply = <&vcc5v>;
+
+	regulators {
+		vrtc_reg: regulator at 0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator at 1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator at 2 {
+			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator at 3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator at 4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator at 5 {
+			regulator-name = "vdig1_1p8v";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vdig2_reg: regulator at 6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator at 7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator at 8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator at 9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator at 10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator at 11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator at 12 {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+/* SPI Busses */
+&am33xx_pinmux {
+	spi0_pins: pinmux_spi0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
+			AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
+		>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+
+	serial_flash: m25p80 at 0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <48000000>;
+		reg = <0x0>;
+		m25p,fast-read;
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
new file mode 100644
index 0000000000..36b761b7bf
--- /dev/null
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+/ {
+	chosen {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootargs = "console=ttyO0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp {
+		u-boot,dm-pre-reloc;
+	};
+
+	memory at 80000000 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+	u-boot,dm-pre-reloc;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts
new file mode 100644
index 0000000000..fe50f3041a
--- /dev/null
+++ b/arch/arm/dts/am335x-wega-rdk.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-wega.dtsi"
+
+/* SoM */
+&i2c_eeprom {
+	status = "okay";
+};
+
+&i2c_rtc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi
new file mode 100644
index 0000000000..f3e045dfc4
--- /dev/null
+++ b/arch/arm/dts/am335x-wega.dtsi
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	model = "Phytec AM335x phyBOARD-WEGA";
+	compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
+
+	sound: sound_iface {
+		compatible = "ti,da830-evm-audio";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		vcc3v3: fixedregulator1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+		};
+	};
+};
+
+/* Audio */
+&am33xx_pinmux {
+	mcasp0_pins: pinmux_mcasp0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
+			AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */
+			AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */
+			AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */
+			AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+		>;
+	};
+};
+
+&i2c0 {
+	tlv320aic3007: tlv320aic3007 at 18 {
+		compatible = "ti,tlv320aic3007";
+		reg = <0x18>;
+		AVDD-supply = <&vcc3v3>;
+		IOVDD-supply = <&vcc3v3>;
+		DRVDD-supply = <&vcc3v3>;
+		DVDD-supply = <&vdig1_reg>;
+		status = "okay";
+	};
+};
+
+&mcasp0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp0_pins>;
+	op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	serial-dir = <
+		2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
+	>;
+	tx-num-evt = <16>;
+	rt-num-evt = <16>;
+	status = "okay";
+};
+
+&sound {
+	ti,model = "AM335x-Wega";
+	ti,audio-codec = <&tlv320aic3007>;
+	ti,mcasp-controller = <&mcasp0>;
+	ti,audio-routing =
+		"Line Out",		"LLOUT",
+		"Line Out",		"RLOUT",
+		"LINE1L",		"Line In",
+		"LINE1R",		"Line In";
+	clocks = <&mcasp0_fck>;
+	clock-names = "mclk";
+	status = "okay";
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+	dcan1_pins: pinmux_dcan1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+			AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+		>;
+	};
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_pins>;
+	status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+	ethernet1_pins: pinmux_ethernet1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
+			AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a9.mii2_rxd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
+			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
+		>;
+	};
+};
+
+&cpsw_emac1 {
+	phy-handle = <&phy1>;
+	phy-mode = "mii";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+};
+
+&mac {
+	slaves = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+	dual_emac = <1>;
+};
+
+/* MMC */
+&am33xx_pinmux {
+	mmc1_pins: pinmux_mmc1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
+		>;
+	};
+};
+
+&mmc1 {
+	vmmc-supply = <&vcc3v3>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+/* Power */
+&vdig1_reg {
+	regulator-boot-on;
+	regulator-always-on;
+};
+
+/* UARTs */
+&am33xx_pinmux {
+	uart0_pins: pinmux_uart0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
+			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
+			AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
+			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
+		>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+/* USB */
+&cppi41dma {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d29f1ca0b5..3fa9dc89b8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
+source "board/phytec/phycore_am335x_r2/Kconfig"
 
 config SPL_LDSCRIPT
         default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 500df1aa11..9da2a16a99 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -177,6 +177,13 @@ config TARGET_PEPPER
 	select DM_SERIAL
 	imply CMD_DM
 
+config TARGET_PHYCORE_AM335X_R2
+	bool "Support phyCORE AM335X R2"
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+	imply CMD_DM
+
 config TARGET_PXM2
 	bool "Support pxm2"
 	select BOARD_LATE_INIT
diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig
new file mode 100644
index 0000000000..77055e043c
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_AM335X_R2
+
+config SYS_BOARD
+	default "phycore_am335x_r2"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "phycore_am335x_r2"
+
+endif
diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS
new file mode 100644
index 0000000000..e56f30fdc0
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -0,0 +1,7 @@
+phyCORE AM335x R2 WEGA BOARD
+M:	Niel Fourie <lusus@denx.de>
+M:	Parthiban Nallathambi <pn@denx.de>
+S:	Maintained
+F:	board/phytec/phycore_am335x_r2
+F:	include/configs/phycore_am335x_r2.h
+F:	configs/phycore-am335x-r2-wega_defconfig
diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile
new file mode 100644
index 0000000000..ff6f8b4221
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
new file mode 100644
index 0000000000..59c44eb284
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <fdtdec.h>
+#include <power/tps65910.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		400 /* DDR_DPLL_MULT value */
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= 0x18B,
+	.cm1ioctl		= 0x18B,
+	.cm2ioctl		= 0x18B,
+	.dt0ioctl		= 0x18B,
+	.dt1ioctl		= 0x18B,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x80,
+	.cmd0iclkout = 0x0,
+
+	.cmd1csratio = 0x80,
+	.cmd1iclkout = 0x0,
+
+	.cmd2csratio = 0x80,
+	.cmd2iclkout = 0x0,
+};
+
+enum {
+	PHYCORE_R2_MT41K128M16JT_256MB,
+	PHYCORE_R2_MT41K256M16TW107IT_512MB,
+	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+};
+
+struct am335x_sdram_timings {
+	struct emif_regs ddr3_emif_reg_data;
+	struct ddr_data ddr3_data;
+};
+
+static struct am335x_sdram_timings physom_timings[] = {
+	[PHYCORE_R2_MT41K128M16JT_256MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C052B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x26437FDA,
+			.sdram_tim3 = 0x501F83FF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x36,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x99,
+			.datawrsratio0 = 0x73,
+		},
+	},
+	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C05332,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x266B7FDA,
+			.sdram_tim3 = 0x501F867F,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x37,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x92,
+			.datawrsratio0 = 0x72,
+		},
+	},
+	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C053B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x268F7FDA,
+			.sdram_tim3 = 0x501F88BF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x38,
+			.datawdsratio0 = 0x4d,
+			.datafwsratio0 = 0x9d,
+			.datawrsratio0 = 0x82,
+		},
+	},
+};
+
+void sdram_init(void)
+{
+	int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+
+	if (fdtdec_setup_mem_size_base())
+		gd->ram_size = SZ_256M;
+
+	switch (gd->ram_size) {
+	case SZ_1G:
+		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+		break;
+	case SZ_512M:
+		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
+		break;
+	case SZ_256M:
+	default:
+		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+		break;
+	}
+
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data, 0);
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
+}
+
+void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
+	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (power_tps65910_init(0))
+		return;
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
+}
+
+void scale_vcores(void)
+{
+	int freq;
+
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+	scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_i2c0_pin_mux();
+	enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif
diff --git a/board/phytec/phycore_am335x_r2/board.h b/board/phytec/phycore_am335x_r2/board.h
new file mode 100644
index 0000000000..68c3d56aa5
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (pcl060) boards information header
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to access the PMIC. We then have a main
+ * pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c
new file mode 100644
index 0000000000..5fd452e66d
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/mux.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
new file mode 100644
index 0000000000..8888d8ff60
--- /dev/null
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=1000
+CONFIG_TARGET_PHYCORE_AM335X_R2=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),512k(NAND.u-boot),512k(NAND.u-boot.backup1),256k(NAND.u-boot-env),-(NAND.UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETHER=y
+# CONFIG_OMAP_WATCHDOG is not set
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
new file mode 100644
index 0000000000..31a07062a0
--- /dev/null
+++ b/include/configs/phycore_am335x_r2.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * phycore_am335x_r2.h
+ *
+ * Phytec phyCORE-AM335x R2 (pcl060) boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef __CONFIG_PHYCORE_AM335x_R2_H
+#define __CONFIG_PHYCORE_AM335x_R2_H
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_ENV_SIZE			SZ_128K
+#define CONFIG_MACH_TYPE		MACH_TYPE_SBC_PHYCORE_AM335X
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \
+	"nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"ubi part NAND.UBI; " \
+		"ubi readvol ${fdtaddr} oftree; " \
+		"ubi readvol ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#else
+#define NANDARGS ""
+#endif
+
+/* set to negative value for no autoboot */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance "; "\
+	"setenv bootpart " #instance ":1 ; "\
+	"setenv rootpart " #instance ":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(NAND, nand, 0)
+
+#include <config_distro_bootcmd.h>
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootfile=zImage\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcrootfstype=ext2 rootwait\0" \
+	"finduuid=part uuid mmc ${rootpart} uuid\0" \
+	"boot_fit=0\0" \
+	NANDARGS \
+	BOOTENV
+
+/* Clock Macros */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				V_OSCK
+
+#define CONFIG_POWER_TPS65910
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/* CPU */
+
+#ifdef CONFIG_SPI_BOOT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		0x000a0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+#endif	/* ! __CONFIG_PHYCORE_AM335x_R2_H */
-- 
2.21.0

^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-06 14:02 [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support Niel Fourie
@ 2019-05-06 14:18 ` Tom Rini
  2019-05-06 16:44   ` Niel Fourie
  0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2019-05-06 14:18 UTC (permalink / raw)
  To: u-boot

On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:

> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> phyBOARD-Wega AM335x.
> 
> CPU  : AM335X-GP rev 2.1
> Model: Phytec AM335x phyBOARD-WEGA
> DRAM:  256 MiB
> NAND:  256 MiB
> MMC:   OMAP SD/MMC: 0
> eth0: ethernet at 4a100000
> 
> Working:
>  - Eth0
>  - i2C
>  - MMC/SD
>  - NAND
>  - UART
>  - USB (host)
> 
> Device trees were taken from Linux mainline:
> commit 37624b58542f ("Linux 5.1-rc7")
> 
> Signed-off-by: Niel Fourie <lusus@denx.de>
[snip]
> +	memory at 80000000 {
> +		u-boot,dm-pre-reloc;
> +	};

You don't need this because:

[snip]
> +void sdram_init(void)
> +{
> +	int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> +
> +	if (fdtdec_setup_mem_size_base())
> +		gd->ram_size = SZ_256M;
> +
> +	switch (gd->ram_size) {
> +	case SZ_1G:
> +		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> +		break;
> +	case SZ_512M:
> +		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> +		break;
> +	case SZ_256M:
> +	default:
> +		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> +		break;
> +	}
> +
> +	config_ddr(DDR_CLK_MHZ, &ioregs,
> +		   &physom_timings[ram_type_index].ddr3_data,
> +		   &ddr3_cmd_ctrl_data,
> +		   &physom_timings[ram_type_index].ddr3_emif_reg_data, 0);
> +}

This is wrong.  sdram_init() is called by
arch/arm/mach-omap2/am33xx/board.c::dram_init() which then sets
gd->ram_size based on what get_ram_size() determines.  So this is all
just a wrapper around how the various parts of the am33xx generations
call some form of config_ddr().  And what you have here is a lot of
unused code about which module provides how much memory.  I assume
there's some run-time method to determine which module you're on and
thus determine that correct parameters to pass in for the chip that's in
use.  If you're not there yet then just make sdram_init() call
config_ddr(...) with the correct enum for the 256M chip and then update
this when you have real detection.

-- 
Tom
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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-06 14:18 ` Tom Rini
@ 2019-05-06 16:44   ` Niel Fourie
  2019-05-06 17:24     ` Tom Rini
  0 siblings, 1 reply; 9+ messages in thread
From: Niel Fourie @ 2019-05-06 16:44 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On 5/6/19 4:18 PM, Tom Rini wrote:
> On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
> 
>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>> phyBOARD-Wega AM335x.
>>
>> CPU  : AM335X-GP rev 2.1
>> Model: Phytec AM335x phyBOARD-WEGA
>> DRAM:  256 MiB
>> NAND:  256 MiB
>> MMC:   OMAP SD/MMC: 0
>> eth0: ethernet at 4a100000
>>
>> Working:
>>   - Eth0
>>   - i2C
>>   - MMC/SD
>>   - NAND
>>   - UART
>>   - USB (host)
>>
>> Device trees were taken from Linux mainline:
>> commit 37624b58542f ("Linux 5.1-rc7")
>>
>> Signed-off-by: Niel Fourie <lusus@denx.de>
>> +void sdram_init(void)
>> +{
>> +	int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
>> +
>> +	if (fdtdec_setup_mem_size_base())
>> +		gd->ram_size = SZ_256M;
>> +
>> +	switch (gd->ram_size) {
>> +	case SZ_1G:
>> +		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>> +		break;
>> +	case SZ_512M:
>> +		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
>> +		break;
>> +	case SZ_256M:
>> +	default:
>> +		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
>> +		break;
>> +	}
>> +
>> +	config_ddr(DDR_CLK_MHZ, &ioregs,
>> +		   &physom_timings[ram_type_index].ddr3_data,
>> +		   &ddr3_cmd_ctrl_data,
>> +		   &physom_timings[ram_type_index].ddr3_emif_reg_data, 0);
>> +}
> 
> This is wrong.  sdram_init() is called by
> arch/arm/mach-omap2/am33xx/board.c::dram_init() which then sets
> gd->ram_size based on what get_ram_size() determines.  So this is all
> just a wrapper around how the various parts of the am33xx generations
> call some form of config_ddr().  And what you have here is a lot of
> unused code about which module provides how much memory.  I assume
> there's some run-time method to determine which module you're on and
> thus determine that correct parameters to pass in for the chip that's in
> use.  If you're not there yet then just make sdram_init() call
> config_ddr(...) with the correct enum for the 256M chip and then update
> this when you have real detection.

Thanks for that input, you are right. I could not find any documented 
way to detect the exact module we are running on, but as you pointed out 
we can use get_ram_size() to find the size of the installed RAM. This is 
in fact exactly what barebox did, I just missed it. How is this for a 
replacement of the above?

void sdram_init(void)
{
	/* Configure memory to maximum supported size for detection */
	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
	config_ddr(DDR_CLK_MHZ, &ioregs,
		   &physom_timings[ram_type_index].ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
		   0);

	/* Detect memory physically present */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_MAX_RAM_BANK_SIZE);

	/* Reconfigure memory for actual detected size */
	switch (gd->ram_size) {
	case SZ_1G:
		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
		break;
	case SZ_512M:
		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
		break;
	case SZ_256M:
	default:
		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
		break;
	}
	config_ddr(DDR_CLK_MHZ, &ioregs,
		   &physom_timings[ram_type_index].ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
		   0);
}

The ugliest part of this is, as you pointed out, that directly after 
this is called, get_ram_size() will be called again from sdram_init(). 
But it at least noninvasive, and no longer requires the device tree.

Best regards,
Niel Fourie

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lusus at denx.de

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-06 16:44   ` Niel Fourie
@ 2019-05-06 17:24     ` Tom Rini
  2019-05-07  9:39       ` Niel Fourie
  0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2019-05-06 17:24 UTC (permalink / raw)
  To: u-boot

On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
> Hi Tom,
> 
> On 5/6/19 4:18 PM, Tom Rini wrote:
> >On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
> >
> >>Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> >>phyBOARD-Wega AM335x.
> >>
> >>CPU  : AM335X-GP rev 2.1
> >>Model: Phytec AM335x phyBOARD-WEGA
> >>DRAM:  256 MiB
> >>NAND:  256 MiB
> >>MMC:   OMAP SD/MMC: 0
> >>eth0: ethernet at 4a100000
> >>
> >>Working:
> >>  - Eth0
> >>  - i2C
> >>  - MMC/SD
> >>  - NAND
> >>  - UART
> >>  - USB (host)
> >>
> >>Device trees were taken from Linux mainline:
> >>commit 37624b58542f ("Linux 5.1-rc7")
> >>
> >>Signed-off-by: Niel Fourie <lusus@denx.de>
> >>+void sdram_init(void)
> >>+{
> >>+	int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> >>+
> >>+	if (fdtdec_setup_mem_size_base())
> >>+		gd->ram_size = SZ_256M;
> >>+
> >>+	switch (gd->ram_size) {
> >>+	case SZ_1G:
> >>+		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> >>+		break;
> >>+	case SZ_512M:
> >>+		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> >>+		break;
> >>+	case SZ_256M:
> >>+	default:
> >>+		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> >>+		break;
> >>+	}
> >>+
> >>+	config_ddr(DDR_CLK_MHZ, &ioregs,
> >>+		   &physom_timings[ram_type_index].ddr3_data,
> >>+		   &ddr3_cmd_ctrl_data,
> >>+		   &physom_timings[ram_type_index].ddr3_emif_reg_data, 0);
> >>+}
> >
> >This is wrong.  sdram_init() is called by
> >arch/arm/mach-omap2/am33xx/board.c::dram_init() which then sets
> >gd->ram_size based on what get_ram_size() determines.  So this is all
> >just a wrapper around how the various parts of the am33xx generations
> >call some form of config_ddr().  And what you have here is a lot of
> >unused code about which module provides how much memory.  I assume
> >there's some run-time method to determine which module you're on and
> >thus determine that correct parameters to pass in for the chip that's in
> >use.  If you're not there yet then just make sdram_init() call
> >config_ddr(...) with the correct enum for the 256M chip and then update
> >this when you have real detection.
> 
> Thanks for that input, you are right. I could not find any documented way to
> detect the exact module we are running on, but as you pointed out we can use
> get_ram_size() to find the size of the installed RAM. This is in fact
> exactly what barebox did, I just missed it. How is this for a replacement of
> the above?
> 
> void sdram_init(void)
> {
> 	/* Configure memory to maximum supported size for detection */
> 	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> 	config_ddr(DDR_CLK_MHZ, &ioregs,
> 		   &physom_timings[ram_type_index].ddr3_data,
> 		   &ddr3_cmd_ctrl_data,
> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> 		   0);
> 
> 	/* Detect memory physically present */
> 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> 				    CONFIG_MAX_RAM_BANK_SIZE);
> 
> 	/* Reconfigure memory for actual detected size */
> 	switch (gd->ram_size) {
> 	case SZ_1G:
> 		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> 		break;
> 	case SZ_512M:
> 		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> 		break;
> 	case SZ_256M:
> 	default:
> 		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> 		break;
> 	}
> 	config_ddr(DDR_CLK_MHZ, &ioregs,
> 		   &physom_timings[ram_type_index].ddr3_data,
> 		   &ddr3_cmd_ctrl_data,
> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> 		   0);
> }
> 
> The ugliest part of this is, as you pointed out, that directly after this is
> called, get_ram_size() will be called again from sdram_init(). But it at
> least noninvasive, and no longer requires the device tree.

I don't think it's safe to call config_ddr twice, especially with the
possibly wrong parameters.  What's barebox doing in this case, being
told the presumably correct DDR size in the device tree?

-- 
Tom
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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-06 17:24     ` Tom Rini
@ 2019-05-07  9:39       ` Niel Fourie
  2019-05-07 13:19         ` Tom Rini
  0 siblings, 1 reply; 9+ messages in thread
From: Niel Fourie @ 2019-05-07  9:39 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On 5/6/19 7:24 PM, Tom Rini wrote:
> On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
>> Hi Tom,
>>
>> On 5/6/19 4:18 PM, Tom Rini wrote:
>>> On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
>>>
>>>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>>>> phyBOARD-Wega AM335x.
>>>>
>>>> CPU  : AM335X-GP rev 2.1
>>>> Model: Phytec AM335x phyBOARD-WEGA
>>>> DRAM:  256 MiB
>>>> NAND:  256 MiB
>>>> MMC:   OMAP SD/MMC: 0
>>>> eth0: ethernet at 4a100000
>>>>
>>>> Working:
>>>>   - Eth0
>>>>   - i2C
>>>>   - MMC/SD
>>>>   - NAND
>>>>   - UART
>>>>   - USB (host)
>>>>
>>>> Device trees were taken from Linux mainline:
>>>> commit 37624b58542f ("Linux 5.1-rc7")
>>>>
>>>> Signed-off-by: Niel Fourie <lusus@denx.de>
[snip]
>>
>> void sdram_init(void)
>> {
>> 	/* Configure memory to maximum supported size for detection */
>> 	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>> 	config_ddr(DDR_CLK_MHZ, &ioregs,
>> 		   &physom_timings[ram_type_index].ddr3_data,
>> 		   &ddr3_cmd_ctrl_data,
>> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
>> 		   0);
>>
>> 	/* Detect memory physically present */
>> 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
>> 				    CONFIG_MAX_RAM_BANK_SIZE);
>>
>> 	/* Reconfigure memory for actual detected size */
>> 	switch (gd->ram_size) {
>> 	case SZ_1G:
>> 		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>> 		break;
>> 	case SZ_512M:
>> 		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
>> 		break;
>> 	case SZ_256M:
>> 	default:
>> 		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
>> 		break;
>> 	}
>> 	config_ddr(DDR_CLK_MHZ, &ioregs,
>> 		   &physom_timings[ram_type_index].ddr3_data,
>> 		   &ddr3_cmd_ctrl_data,
>> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
>> 		   0);
>> }
>>
>> The ugliest part of this is, as you pointed out, that directly after this is
>> called, get_ram_size() will be called again from sdram_init(). But it at
>> least noninvasive, and no longer requires the device tree.
> 
> I don't think it's safe to call config_ddr twice, especially with the
> possibly wrong parameters.  What's barebox doing in this case, being
> told the presumably correct DDR size in the device tree?

Good point. Barebox uses the above mechanism to detect the memory size, 
and I could find no equivalent memory size specified in its internal 
device tree.

Marek originally proposed using the memory size specified in the device 
tree as an improvement over specifying the size in the defconfig (as in 
v1 of the patch).

Best regards,
Niel Fourie

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lusus at denx.de

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-07  9:39       ` Niel Fourie
@ 2019-05-07 13:19         ` Tom Rini
  2019-05-07 14:43           ` Niel Fourie
  0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2019-05-07 13:19 UTC (permalink / raw)
  To: u-boot

On Tue, May 07, 2019 at 11:39:12AM +0200, Niel Fourie wrote:
> Hi Tom,
> 
> On 5/6/19 7:24 PM, Tom Rini wrote:
> >On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
> >>Hi Tom,
> >>
> >>On 5/6/19 4:18 PM, Tom Rini wrote:
> >>>On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
> >>>
> >>>>Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> >>>>phyBOARD-Wega AM335x.
> >>>>
> >>>>CPU  : AM335X-GP rev 2.1
> >>>>Model: Phytec AM335x phyBOARD-WEGA
> >>>>DRAM:  256 MiB
> >>>>NAND:  256 MiB
> >>>>MMC:   OMAP SD/MMC: 0
> >>>>eth0: ethernet at 4a100000
> >>>>
> >>>>Working:
> >>>>  - Eth0
> >>>>  - i2C
> >>>>  - MMC/SD
> >>>>  - NAND
> >>>>  - UART
> >>>>  - USB (host)
> >>>>
> >>>>Device trees were taken from Linux mainline:
> >>>>commit 37624b58542f ("Linux 5.1-rc7")
> >>>>
> >>>>Signed-off-by: Niel Fourie <lusus@denx.de>
> [snip]
> >>
> >>void sdram_init(void)
> >>{
> >>	/* Configure memory to maximum supported size for detection */
> >>	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> >>	config_ddr(DDR_CLK_MHZ, &ioregs,
> >>		   &physom_timings[ram_type_index].ddr3_data,
> >>		   &ddr3_cmd_ctrl_data,
> >>		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> >>		   0);
> >>
> >>	/* Detect memory physically present */
> >>	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> >>				    CONFIG_MAX_RAM_BANK_SIZE);
> >>
> >>	/* Reconfigure memory for actual detected size */
> >>	switch (gd->ram_size) {
> >>	case SZ_1G:
> >>		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> >>		break;
> >>	case SZ_512M:
> >>		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> >>		break;
> >>	case SZ_256M:
> >>	default:
> >>		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> >>		break;
> >>	}
> >>	config_ddr(DDR_CLK_MHZ, &ioregs,
> >>		   &physom_timings[ram_type_index].ddr3_data,
> >>		   &ddr3_cmd_ctrl_data,
> >>		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> >>		   0);
> >>}
> >>
> >>The ugliest part of this is, as you pointed out, that directly after this is
> >>called, get_ram_size() will be called again from sdram_init(). But it at
> >>least noninvasive, and no longer requires the device tree.
> >
> >I don't think it's safe to call config_ddr twice, especially with the
> >possibly wrong parameters.  What's barebox doing in this case, being
> >told the presumably correct DDR size in the device tree?
> 
> Good point. Barebox uses the above mechanism to detect the memory size, and
> I could find no equivalent memory size specified in its internal device
> tree.

Configure for 1GB and then see how much we can actually talk to?

> Marek originally proposed using the memory size specified in the device tree
> as an improvement over specifying the size in the defconfig (as in v1 of the
> patch).

But then you aren't populating 3 device trees nor making it clear / easy
to say which module you're on, and then still need to change the config
for which DT you're picking up.  These SOMs really don't provide any
run-time method to see which one you're on?  There's no GPIOs to poke?

-- 
Tom
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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-07 13:19         ` Tom Rini
@ 2019-05-07 14:43           ` Niel Fourie
  2019-05-07 15:05             ` Tom Rini
  2019-05-09  9:11             ` Wadim Egorov
  0 siblings, 2 replies; 9+ messages in thread
From: Niel Fourie @ 2019-05-07 14:43 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On 5/7/19 3:19 PM, Tom Rini wrote:
> On Tue, May 07, 2019 at 11:39:12AM +0200, Niel Fourie wrote:
>> Hi Tom,
>>
>> On 5/6/19 7:24 PM, Tom Rini wrote:
>>> On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
>>>> Hi Tom,
>>>>
>>>> On 5/6/19 4:18 PM, Tom Rini wrote:
>>>>> On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
>>>>>
>>>>>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>>>>>> phyBOARD-Wega AM335x.
>>>>>>
>>>>>> CPU  : AM335X-GP rev 2.1
>>>>>> Model: Phytec AM335x phyBOARD-WEGA
>>>>>> DRAM:  256 MiB
>>>>>> NAND:  256 MiB
>>>>>> MMC:   OMAP SD/MMC: 0
>>>>>> eth0: ethernet at 4a100000
>>>>>>
>>>>>> Working:
>>>>>>   - Eth0
>>>>>>   - i2C
>>>>>>   - MMC/SD
>>>>>>   - NAND
>>>>>>   - UART
>>>>>>   - USB (host)
>>>>>>
>>>>>> Device trees were taken from Linux mainline:
>>>>>> commit 37624b58542f ("Linux 5.1-rc7")
>>>>>>
>>>>>> Signed-off-by: Niel Fourie <lusus@denx.de>
>> [snip]
>>>>
>>>> void sdram_init(void)
>>>> {
>>>> 	/* Configure memory to maximum supported size for detection */
>>>> 	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>>>> 	config_ddr(DDR_CLK_MHZ, &ioregs,
>>>> 		   &physom_timings[ram_type_index].ddr3_data,
>>>> 		   &ddr3_cmd_ctrl_data,
>>>> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
>>>> 		   0);
>>>>
>>>> 	/* Detect memory physically present */
>>>> 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
>>>> 				    CONFIG_MAX_RAM_BANK_SIZE);
>>>>
>>>> 	/* Reconfigure memory for actual detected size */
>>>> 	switch (gd->ram_size) {
>>>> 	case SZ_1G:
>>>> 		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>>>> 		break;
>>>> 	case SZ_512M:
>>>> 		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
>>>> 		break;
>>>> 	case SZ_256M:
>>>> 	default:
>>>> 		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
>>>> 		break;
>>>> 	}
>>>> 	config_ddr(DDR_CLK_MHZ, &ioregs,
>>>> 		   &physom_timings[ram_type_index].ddr3_data,
>>>> 		   &ddr3_cmd_ctrl_data,
>>>> 		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
>>>> 		   0);
>>>> }
>>>>
>>>> The ugliest part of this is, as you pointed out, that directly after this is
>>>> called, get_ram_size() will be called again from sdram_init(). But it at
>>>> least noninvasive, and no longer requires the device tree.
>>>
>>> I don't think it's safe to call config_ddr twice, especially with the
>>> possibly wrong parameters.  What's barebox doing in this case, being
>>> told the presumably correct DDR size in the device tree?
>>
>> Good point. Barebox uses the above mechanism to detect the memory size, and
>> I could find no equivalent memory size specified in its internal device
>> tree.
> 
> Configure for 1GB and then see how much we can actually talk to?

Yes. If you are interested, you can see their implementation here [1], 
where get_minimal_timings() returns the configuration for 1GiB; 
everything is in that file. (I did credit the author.)

[1] 
https://git.pengutronix.de/cgit/barebox/tree/arch/arm/boards/phytec-som-am335x/lowlevel.c#n167

>> Marek originally proposed using the memory size specified in the device tree
>> as an improvement over specifying the size in the defconfig (as in v1 of the
>> patch).
> 
> But then you aren't populating 3 device trees nor making it clear / easy
> to say which module you're on, and then still need to change the config
> for which DT you're picking up.  These SOMs really don't provide any
> run-time method to see which one you're on?  There's no GPIOs to poke?

Agreed, the device tree solution is inferior to autodetection. The SOMs 
manual makes no mention of how different variants can be 
distinguished/detected, and the board specific code in Barebox (written 
by Phytec) does not contain any other detection code (except for the 
RAM), like checking GPIOs. Unfortunately there is no publicly available 
schematic, so I can't be completely sure. So I am going to assume it, 
there is no other way of detection.

Best regards,
Niel Fourie

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lusus at denx.de

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-07 14:43           ` Niel Fourie
@ 2019-05-07 15:05             ` Tom Rini
  2019-05-09  9:11             ` Wadim Egorov
  1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2019-05-07 15:05 UTC (permalink / raw)
  To: u-boot

On Tue, May 07, 2019 at 04:43:04PM +0200, Niel Fourie wrote:
> Hi Tom,
> 
> On 5/7/19 3:19 PM, Tom Rini wrote:
> >On Tue, May 07, 2019 at 11:39:12AM +0200, Niel Fourie wrote:
> >>Hi Tom,
> >>
> >>On 5/6/19 7:24 PM, Tom Rini wrote:
> >>>On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
> >>>>Hi Tom,
> >>>>
> >>>>On 5/6/19 4:18 PM, Tom Rini wrote:
> >>>>>On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
> >>>>>
> >>>>>>Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> >>>>>>phyBOARD-Wega AM335x.
> >>>>>>
> >>>>>>CPU  : AM335X-GP rev 2.1
> >>>>>>Model: Phytec AM335x phyBOARD-WEGA
> >>>>>>DRAM:  256 MiB
> >>>>>>NAND:  256 MiB
> >>>>>>MMC:   OMAP SD/MMC: 0
> >>>>>>eth0: ethernet at 4a100000
> >>>>>>
> >>>>>>Working:
> >>>>>>  - Eth0
> >>>>>>  - i2C
> >>>>>>  - MMC/SD
> >>>>>>  - NAND
> >>>>>>  - UART
> >>>>>>  - USB (host)
> >>>>>>
> >>>>>>Device trees were taken from Linux mainline:
> >>>>>>commit 37624b58542f ("Linux 5.1-rc7")
> >>>>>>
> >>>>>>Signed-off-by: Niel Fourie <lusus@denx.de>
> >>[snip]
> >>>>
> >>>>void sdram_init(void)
> >>>>{
> >>>>	/* Configure memory to maximum supported size for detection */
> >>>>	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> >>>>	config_ddr(DDR_CLK_MHZ, &ioregs,
> >>>>		   &physom_timings[ram_type_index].ddr3_data,
> >>>>		   &ddr3_cmd_ctrl_data,
> >>>>		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> >>>>		   0);
> >>>>
> >>>>	/* Detect memory physically present */
> >>>>	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> >>>>				    CONFIG_MAX_RAM_BANK_SIZE);
> >>>>
> >>>>	/* Reconfigure memory for actual detected size */
> >>>>	switch (gd->ram_size) {
> >>>>	case SZ_1G:
> >>>>		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> >>>>		break;
> >>>>	case SZ_512M:
> >>>>		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> >>>>		break;
> >>>>	case SZ_256M:
> >>>>	default:
> >>>>		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> >>>>		break;
> >>>>	}
> >>>>	config_ddr(DDR_CLK_MHZ, &ioregs,
> >>>>		   &physom_timings[ram_type_index].ddr3_data,
> >>>>		   &ddr3_cmd_ctrl_data,
> >>>>		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
> >>>>		   0);
> >>>>}
> >>>>
> >>>>The ugliest part of this is, as you pointed out, that directly after this is
> >>>>called, get_ram_size() will be called again from sdram_init(). But it at
> >>>>least noninvasive, and no longer requires the device tree.
> >>>
> >>>I don't think it's safe to call config_ddr twice, especially with the
> >>>possibly wrong parameters.  What's barebox doing in this case, being
> >>>told the presumably correct DDR size in the device tree?
> >>
> >>Good point. Barebox uses the above mechanism to detect the memory size, and
> >>I could find no equivalent memory size specified in its internal device
> >>tree.
> >
> >Configure for 1GB and then see how much we can actually talk to?
> 
> Yes. If you are interested, you can see their implementation here [1], where
> get_minimal_timings() returns the configuration for 1GiB; everything is in
> that file. (I did credit the author.)
> 
> [1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/boards/phytec-som-am335x/lowlevel.c#n167

Thinking back to my time at TI, that leaves me a little worried, but if
the vendor is OK with that approach, I'll leave it be, and yes, we can
mirror that approach here.  Thanks for the links!

-- 
Tom
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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support
  2019-05-07 14:43           ` Niel Fourie
  2019-05-07 15:05             ` Tom Rini
@ 2019-05-09  9:11             ` Wadim Egorov
  1 sibling, 0 replies; 9+ messages in thread
From: Wadim Egorov @ 2019-05-09  9:11 UTC (permalink / raw)
  To: u-boot


On 07.05.19 16:43, Niel Fourie wrote:
> Hi Tom,
>
> On 5/7/19 3:19 PM, Tom Rini wrote:
>> On Tue, May 07, 2019 at 11:39:12AM +0200, Niel Fourie wrote:
>>> Hi Tom,
>>>
>>> On 5/6/19 7:24 PM, Tom Rini wrote:
>>>> On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
>>>>> Hi Tom,
>>>>>
>>>>> On 5/6/19 4:18 PM, Tom Rini wrote:
>>>>>> On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
>>>>>>
>>>>>>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>>>>>>> phyBOARD-Wega AM335x.
>>>>>>>
>>>>>>> CPU  : AM335X-GP rev 2.1
>>>>>>> Model: Phytec AM335x phyBOARD-WEGA
>>>>>>> DRAM:  256 MiB
>>>>>>> NAND:  256 MiB
>>>>>>> MMC:   OMAP SD/MMC: 0
>>>>>>> eth0: ethernet at 4a100000
>>>>>>>
>>>>>>> Working:
>>>>>>>   - Eth0
>>>>>>>   - i2C
>>>>>>>   - MMC/SD
>>>>>>>   - NAND
>>>>>>>   - UART
>>>>>>>   - USB (host)
>>>>>>>
>>>>>>> Device trees were taken from Linux mainline:
>>>>>>> commit 37624b58542f ("Linux 5.1-rc7")
>>>>>>>
>>>>>>> Signed-off-by: Niel Fourie <lusus@denx.de>
>>> [snip]
>>>>>
>>>>> void sdram_init(void)
>>>>> {
>>>>>     /* Configure memory to maximum supported size for detection */
>>>>>     int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>>>>>     config_ddr(DDR_CLK_MHZ, &ioregs,
>>>>>            &physom_timings[ram_type_index].ddr3_data,
>>>>>            &ddr3_cmd_ctrl_data,
>>>>>            &physom_timings[ram_type_index].ddr3_emif_reg_data,
>>>>>            0);
>>>>>
>>>>>     /* Detect memory physically present */
>>>>>     gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
>>>>>                     CONFIG_MAX_RAM_BANK_SIZE);
>>>>>
>>>>>     /* Reconfigure memory for actual detected size */
>>>>>     switch (gd->ram_size) {
>>>>>     case SZ_1G:
>>>>>         ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
>>>>>         break;
>>>>>     case SZ_512M:
>>>>>         ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
>>>>>         break;
>>>>>     case SZ_256M:
>>>>>     default:
>>>>>         ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
>>>>>         break;
>>>>>     }
>>>>>     config_ddr(DDR_CLK_MHZ, &ioregs,
>>>>>            &physom_timings[ram_type_index].ddr3_data,
>>>>>            &ddr3_cmd_ctrl_data,
>>>>>            &physom_timings[ram_type_index].ddr3_emif_reg_data,
>>>>>            0);
>>>>> }
>>>>>
>>>>> The ugliest part of this is, as you pointed out, that directly
>>>>> after this is
>>>>> called, get_ram_size() will be called again from sdram_init(). But
>>>>> it at
>>>>> least noninvasive, and no longer requires the device tree.
>>>>
>>>> I don't think it's safe to call config_ddr twice, especially with the
>>>> possibly wrong parameters.  What's barebox doing in this case, being
>>>> told the presumably correct DDR size in the device tree?
>>>
>>> Good point. Barebox uses the above mechanism to detect the memory
>>> size, and
>>> I could find no equivalent memory size specified in its internal device
>>> tree.
>>
>> Configure for 1GB and then see how much we can actually talk to?
>
> Yes. If you are interested, you can see their implementation here [1],
> where get_minimal_timings() returns the configuration for 1GiB;
> everything is in that file. (I did credit the author.)
>
> [1]
> https://git.pengutronix.de/cgit/barebox/tree/arch/arm/boards/phytec-som-am335x/lowlevel.c#n167
>
>>> Marek originally proposed using the memory size specified in the
>>> device tree
>>> as an improvement over specifying the size in the defconfig (as in
>>> v1 of the
>>> patch).
>>
>> But then you aren't populating 3 device trees nor making it clear / easy
>> to say which module you're on, and then still need to change the config
>> for which DT you're picking up.  These SOMs really don't provide any
>> run-time method to see which one you're on?  There's no GPIOs to poke?
>
> Agreed, the device tree solution is inferior to autodetection. The
> SOMs manual makes no mention of how different variants can be
> distinguished/detected, and the board specific code in Barebox
> (written by Phytec) does not contain any other detection code (except
> for the RAM), like checking GPIOs. Unfortunately there is no publicly
> available schematic, so I can't be completely sure. So I am going to
> assume it, there is no other way of detection.

You are right, for our AM335 based SOMs there is no way to detect the
variant. The barebox generates for every possible RAM configuration an
own MLO. The nice thing is that barebox generates all variants with one
build by using its multi image mechanism.

Besides the RAM, the phyCORE can be populated with different AM335x
variants, NANDs, RTC/EEPROM/Eth-PHY(yes/no) and maybe other things I
don't remember now.

I think it would be a good Idea to maintain a list of article numbers
(that fully describes the SOM variant) which are supported by the
current u-boot version.

Regards,
Wadim

>
> Best regards,
> Niel Fourie
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2019-05-09  9:11 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-06 14:02 [U-Boot] [PATCH v5] ARM: am335x: Add phyCORE AM335x R2 support Niel Fourie
2019-05-06 14:18 ` Tom Rini
2019-05-06 16:44   ` Niel Fourie
2019-05-06 17:24     ` Tom Rini
2019-05-07  9:39       ` Niel Fourie
2019-05-07 13:19         ` Tom Rini
2019-05-07 14:43           ` Niel Fourie
2019-05-07 15:05             ` Tom Rini
2019-05-09  9:11             ` Wadim Egorov

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