From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD48C04AAD for ; Tue, 7 May 2019 13:32:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7249C206A3 for ; Tue, 7 May 2019 13:32:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="XafYI8wZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726760AbfEGNcZ (ORCPT ); Tue, 7 May 2019 09:32:25 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:56952 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726321AbfEGNcZ (ORCPT ); Tue, 7 May 2019 09:32:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=42YzfIkNTk2bk5895j/W3Ma7gIDhAlzcSAcyLA3vwr8=; b=XafYI8wZ4ZQn0vOhGSCp4A3Y9 gbrLmqOwPHAqtYd5TT83L8EU1RQsUqDZQaX87iECkQJWeqHG0MnxKzAAcbNrPBg4A+k79zV32IOsL TBevSfqa0L0uo1m130yHTyT6f1P0K1f+I+rktJ0BmHU5J1O6ggjAD0QZDAPYjexdxv6FwNV2Evkti l+7E37dIOCiJjt5VWSF/7hNPExqZJHzvsoAP3g1a66RJnqCVRW36RMNlkoTi+6vx9sy3EjYIoyHIz n63mU3k0uQHXEDHdLC9WfCP4GBMzEf6jXnbPbaSJjC9+cCKH9HENOMlo5T6sA2yvT+LTSznePDvA8 aMbeUPDGg==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1hO0CQ-0002vV-BG; Tue, 07 May 2019 13:32:03 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 5546B2023ADB5; Tue, 7 May 2019 15:32:00 +0200 (CEST) Date: Tue, 7 May 2019 15:32:00 +0200 From: Peter Zijlstra To: David Laight Cc: Linus Torvalds , Andy Lutomirski , Steven Rostedt , Linux List Kernel Mailing , Ingo Molnar , Andrew Morton , Andy Lutomirski , Nicolai Stange , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , the arch/x86 maintainers , Josh Poimboeuf , Jiri Kosina , Miroslav Benes , Petr Mladek , Joe Lawrence , Shuah Khan , Konrad Rzeszutek Wilk , Tim Chen , Sebastian Andrzej Siewior , Mimi Zohar , Juergen Gross , Nick Desaulniers , Nayna Jain , Masahiro Yamada , Joerg Roedel , "open list:KERNEL SELFTEST FRAMEWORK" , stable Subject: Re: [RFC][PATCH 1/2] x86: Allow breakpoints to emulate call functions Message-ID: <20190507133200.GP2623@hirez.programming.kicks-ass.net> References: <20190502195052.0af473cf@gandalf.local.home> <20190503092959.GB2623@hirez.programming.kicks-ass.net> <20190503092247.20cc1ff0@gandalf.local.home> <2045370D-38D8-406C-9E94-C1D483E232C9@amacapital.net> <20190506081951.GJ2606@hirez.programming.kicks-ass.net> <20190507085753.GO2606@hirez.programming.kicks-ass.net> <20190507113050.GR2606@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 07, 2019 at 12:57:15PM +0000, David Laight wrote: > > Only the INT3 thing needs 'the gap', but the far bigger change here is > > that kernel frames now have a complete pt_regs set and all sorts of > > horrible crap can go away. > > I'm not doubting that generating the 'five register' interrupt stack frame > for faults in kernel space makes life simpler just suggesting that the > 'emulated call' can be done by emulating the 'iret' rather than generating > a gap in the stack. The thing you suggested doesn't actually work, INT3 can nest. > > For 32bit 'the gap' happens naturally when building a 5 entry frame. Yes > > it is possible to build a 5 entry frame on top of the old 3 entry one, > > but why bother... > > Presumably there is 'horrid' code to generate the gap in 64bit mode? > (less horrid than 32bit, but still horrid?) > Or does it copy the entire pt_regs into a local stack frame and use > that for the iret? It's in the patch you replied to; it is so small you might have overlooked it. It simply pushes another copy on top of what was already there. > I've just tried to parse the pseudo code for IRET in the intel docs. > Does anyone find that readable? No; it's abysmal. > I wonder if you can force 32bit mode to do a stack switch 'iret' > by doing something like a far jump to a different %cs ? I don't think that'll work. From mboxrd@z Thu Jan 1 00:00:00 1970 From: peterz at infradead.org (Peter Zijlstra) Date: Tue, 7 May 2019 15:32:00 +0200 Subject: [RFC][PATCH 1/2] x86: Allow breakpoints to emulate call functions In-Reply-To: References: <20190502195052.0af473cf@gandalf.local.home> <20190503092959.GB2623@hirez.programming.kicks-ass.net> <20190503092247.20cc1ff0@gandalf.local.home> <2045370D-38D8-406C-9E94-C1D483E232C9@amacapital.net> <20190506081951.GJ2606@hirez.programming.kicks-ass.net> <20190507085753.GO2606@hirez.programming.kicks-ass.net> <20190507113050.GR2606@hirez.programming.kicks-ass.net> Message-ID: <20190507133200.GP2623@hirez.programming.kicks-ass.net> On Tue, May 07, 2019 at 12:57:15PM +0000, David Laight wrote: > > Only the INT3 thing needs 'the gap', but the far bigger change here is > > that kernel frames now have a complete pt_regs set and all sorts of > > horrible crap can go away. > > I'm not doubting that generating the 'five register' interrupt stack frame > for faults in kernel space makes life simpler just suggesting that the > 'emulated call' can be done by emulating the 'iret' rather than generating > a gap in the stack. The thing you suggested doesn't actually work, INT3 can nest. > > For 32bit 'the gap' happens naturally when building a 5 entry frame. Yes > > it is possible to build a 5 entry frame on top of the old 3 entry one, > > but why bother... > > Presumably there is 'horrid' code to generate the gap in 64bit mode? > (less horrid than 32bit, but still horrid?) > Or does it copy the entire pt_regs into a local stack frame and use > that for the iret? It's in the patch you replied to; it is so small you might have overlooked it. It simply pushes another copy on top of what was already there. > I've just tried to parse the pseudo code for IRET in the intel docs. > Does anyone find that readable? No; it's abysmal. > I wonder if you can force 32bit mode to do a stack switch 'iret' > by doing something like a far jump to a different %cs ? I don't think that'll work. From mboxrd@z Thu Jan 1 00:00:00 1970 From: peterz@infradead.org (Peter Zijlstra) Date: Tue, 7 May 2019 15:32:00 +0200 Subject: [RFC][PATCH 1/2] x86: Allow breakpoints to emulate call functions In-Reply-To: References: <20190502195052.0af473cf@gandalf.local.home> <20190503092959.GB2623@hirez.programming.kicks-ass.net> <20190503092247.20cc1ff0@gandalf.local.home> <2045370D-38D8-406C-9E94-C1D483E232C9@amacapital.net> <20190506081951.GJ2606@hirez.programming.kicks-ass.net> <20190507085753.GO2606@hirez.programming.kicks-ass.net> <20190507113050.GR2606@hirez.programming.kicks-ass.net> Message-ID: <20190507133200.GP2623@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Message-ID: <20190507133200.ii9O7q8LjrS3cxnlOcZQkUCebEgoBlqnUMpvSeSDRzg@z> On Tue, May 07, 2019@12:57:15PM +0000, David Laight wrote: > > Only the INT3 thing needs 'the gap', but the far bigger change here is > > that kernel frames now have a complete pt_regs set and all sorts of > > horrible crap can go away. > > I'm not doubting that generating the 'five register' interrupt stack frame > for faults in kernel space makes life simpler just suggesting that the > 'emulated call' can be done by emulating the 'iret' rather than generating > a gap in the stack. The thing you suggested doesn't actually work, INT3 can nest. > > For 32bit 'the gap' happens naturally when building a 5 entry frame. Yes > > it is possible to build a 5 entry frame on top of the old 3 entry one, > > but why bother... > > Presumably there is 'horrid' code to generate the gap in 64bit mode? > (less horrid than 32bit, but still horrid?) > Or does it copy the entire pt_regs into a local stack frame and use > that for the iret? It's in the patch you replied to; it is so small you might have overlooked it. It simply pushes another copy on top of what was already there. > I've just tried to parse the pseudo code for IRET in the intel docs. > Does anyone find that readable? No; it's abysmal. > I wonder if you can force 32bit mode to do a stack switch 'iret' > by doing something like a far jump to a different %cs ? I don't think that'll work.