[U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC

[Yinbo Zhu <yinbo.zhu@nxp.com>]

From: Yangbo Lu <yangbo.lu@nxp.com>

Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
Change in v4:
		Update the Copyright

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 3 ++-
 arch/arm/include/asm/arch-fsl-layerscape/clock.h    | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index bc268e207c..0985778ff9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, 2018 Freescale Semiconductor, Inc.
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -214,6 +214,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
 	case MXC_ESDHC_CLK:
+	case MXC_ESDHC2_CLK:
 		return get_sdhc_freq(0);
 #endif
 	case MXC_DSPI_CLK:
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index cf058d22a9..c6e382b41b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2015, 2018 Freescale Semiconductor, Inc.
  *
  */
 
@@ -14,6 +14,7 @@ enum mxc_clock {
 	MXC_BUS_CLK,
 	MXC_UART_CLK,
 	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
 	MXC_I2C_CLK,
 	MXC_DSPI_CLK,
 };
-- 
2.17.1