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[69.222.133.165]) by smtp.gmail.com with ESMTPSA id u73sm2480260ywf.62.2019.05.17.15.45.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 15:45:14 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:44:44 -0400 Message-Id: <20190517224450.15566-6-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517224450.15566-1-jan.bobek@gmail.com> References: <20190517224450.15566-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU v2 05/11] risu_i386: implement missing CPU-specific functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" risu_i386.c is expected to implement the following functions: - advance_pc - get_reginfo_paramreg, set_ucontext_paramreg - get_risuop - get_pc This patch adds the necessary code. We use EAX as the parameter register and opcode "UD1 %xxx,%eax" for triggering RISU actions. Suggested-by: Richard Henderson Signed-off-by: Jan Bobek --- risu_i386.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/risu_i386.c b/risu_i386.c index 2d2f325..06d95e5 100644 --- a/risu_i386.c +++ b/risu_i386.c @@ -25,12 +25,37 @@ static int insn_is_ud2(uint32_t insn) void advance_pc(void *vuc) { - /* We assume that this is either UD1 or UD2. - * This would need tweaking if we want to test - * expected undefs on x86. + ucontext_t *uc = (ucontext_t *) vuc; + + /* + * We assume that this is UD1 as per get_risuop below. + * This would need tweaking if we want to test expected undefs. */ - ucontext_t *uc = vuc; - uc->uc_mcontext.gregs[REG_EIP] += 2; + uc->uc_mcontext.gregs[REG_E(IP)] += 3; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc = (ucontext_t *) vuc; + uc->uc_mcontext.gregs[REG_E(AX)] = value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->gregs[REG_E(AX)]; +} + +int get_risuop(struct reginfo *ri) +{ + if ((ri->faulting_insn & 0xf8ffff) == 0xc0b90f) { /* UD1 %xxx,%eax */ + return (ri->faulting_insn >> 16) & 7; + } + return -1; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->gregs[REG_E(IP)]; } int send_register_info(int sock, void *uc) -- 2.20.1