From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C8B3C04AB4 for ; Tue, 21 May 2019 10:47:29 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55289216B7 for ; Tue, 21 May 2019 10:47:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55289216B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=cl.cam.ac.uk Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([127.0.0.1]:51230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hT2Iq-00069O-Hr for qemu-devel@archiver.kernel.org; Tue, 21 May 2019 06:47:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hT2Fj-0003So-Sq for qemu-devel@nongnu.org; Tue, 21 May 2019 06:44:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hT2Fi-0003Ln-SC for qemu-devel@nongnu.org; Tue, 21 May 2019 06:44:15 -0400 Received: from mta1.cl.cam.ac.uk ([2a05:b400:110::25:1]:36729) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hT2Fg-0003EF-Iz; Tue, 21 May 2019 06:44:12 -0400 Received: from cassia.cl.cam.ac.uk ([2001:630:212:238:b26e:bfff:fe2f:c7d9]) by mta1.cl.cam.ac.uk with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1hT2Ff-000163-LQ; Tue, 21 May 2019 10:44:11 +0000 Received: from hmka2 by cassia.cl.cam.ac.uk with local (Exim 4.90_1) (envelope-from ) id 1hT2Ff-0003ex-J8; Tue, 21 May 2019 11:44:11 +0100 From: Hesham Almatary To: qemu-riscv@nongnu.org Date: Tue, 21 May 2019 11:43:21 +0100 Message-Id: <20190521104324.12835-2-Hesham.Almatary@cl.cam.ac.uk> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190521104324.12835-1-Hesham.Almatary@cl.cam.ac.uk> References: <20190521104324.12835-1-Hesham.Almatary@cl.cam.ac.uk> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a05:b400:110::25:1 Subject: [Qemu-devel] [PATCHv3 2/5] RISC-V: Raise access fault exceptions on PMP violations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Hesham Almatary Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Reviewed-by: Alistair Francis Signed-off-by: Hesham Almatary --- target/riscv/cpu_helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 40fb47e794..7c7282c680 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -318,12 +318,13 @@ restart: } static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, bool pmp_violation) { CPUState *cs = CPU(riscv_env_get_cpu(env)); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && + !pmp_violation; switch (access_type) { case MMU_INST_FETCH: cs->exception_index = page_fault_exceptions ? @@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPURISCVState *env = &cpu->env; hwaddr pa = 0; int prot; + bool pmp_violation = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", @@ -403,6 +405,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + pmp_violation = true; ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { @@ -412,7 +415,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type); + raise_mmu_exception(env, address, access_type, pmp_violation); riscv_raise_exception(env, cs->exception_index, retaddr); } #else -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1hT2Fj-0003SX-KO for mharc-qemu-riscv@gnu.org; Tue, 21 May 2019 06:44:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hT2Fh-0003RI-Pt for qemu-riscv@nongnu.org; Tue, 21 May 2019 06:44:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hT2Fg-0003FA-OT for qemu-riscv@nongnu.org; Tue, 21 May 2019 06:44:13 -0400 Received: from mta1.cl.cam.ac.uk ([2a05:b400:110::25:1]:36729) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hT2Fg-0003EF-Iz; Tue, 21 May 2019 06:44:12 -0400 Received: from cassia.cl.cam.ac.uk ([2001:630:212:238:b26e:bfff:fe2f:c7d9]) by mta1.cl.cam.ac.uk with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1hT2Ff-000163-LQ; Tue, 21 May 2019 10:44:11 +0000 Received: from hmka2 by cassia.cl.cam.ac.uk with local (Exim 4.90_1) (envelope-from ) id 1hT2Ff-0003ex-J8; Tue, 21 May 2019 11:44:11 +0100 From: Hesham Almatary To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Hesham Almatary , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Date: Tue, 21 May 2019 11:43:21 +0100 Message-Id: <20190521104324.12835-2-Hesham.Almatary@cl.cam.ac.uk> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190521104324.12835-1-Hesham.Almatary@cl.cam.ac.uk> References: <20190521104324.12835-1-Hesham.Almatary@cl.cam.ac.uk> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a05:b400:110::25:1 Subject: [Qemu-riscv] [PATCHv3 2/5] RISC-V: Raise access fault exceptions on PMP violations X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 May 2019 10:44:14 -0000 Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Reviewed-by: Alistair Francis Signed-off-by: Hesham Almatary --- target/riscv/cpu_helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 40fb47e794..7c7282c680 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -318,12 +318,13 @@ restart: } static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, bool pmp_violation) { CPUState *cs = CPU(riscv_env_get_cpu(env)); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && + !pmp_violation; switch (access_type) { case MMU_INST_FETCH: cs->exception_index = page_fault_exceptions ? @@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPURISCVState *env = &cpu->env; hwaddr pa = 0; int prot; + bool pmp_violation = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", @@ -403,6 +405,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + pmp_violation = true; ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { @@ -412,7 +415,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type); + raise_mmu_exception(env, address, access_type, pmp_violation); riscv_raise_exception(env, cs->exception_index, retaddr); } #else -- 2.17.1