From: Faiz Abbas <faiz_abbas@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 11/15] mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings
Date: Thu, 23 May 2019 12:37:48 -0500 [thread overview]
Message-ID: <20190523173752.28680-12-faiz_abbas@ti.com> (raw)
In-Reply-To: <20190523173752.28680-1-faiz_abbas@ti.com>
From: Faiz Abbas <faiz4000@gmail.com>
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.
Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas <faiz4000@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
drivers/mmc/sdhci.c | 28 ++++++++++++++++++++++++++++
drivers/mmc/zynq_sdhci.c | 31 ++-----------------------------
include/sdhci.h | 19 ++++++++++++++++++-
3 files changed, 48 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 75e6567631..79edb18fe5 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -533,6 +533,34 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
+void sdhci_set_uhs_timing(struct sdhci_host *host)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 reg;
+
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_UHS_MASK;
+
+ switch (mmc->selected_mode) {
+ case UHS_SDR50:
+ case MMC_HS_52:
+ reg |= SDHCI_CTRL_UHS_SDR50;
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ reg |= SDHCI_CTRL_UHS_DDR50;
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ default:
+ reg |= SDHCI_CTRL_UHS_SDR12;
+ }
+
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 08023783de..b39e1d7a19 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -48,11 +48,6 @@ static const u8 mode2timing[] = {
[MMC_HS_200] = MMC_HS200_BUS_SPEED,
};
-#define SDHCI_HOST_CTRL2 0x3E
-#define SDHCI_CTRL2_MODE_MASK 0x7
-#define SDHCI_18V_SIGNAL 0x8
-#define SDHCI_CTRL_EXEC_TUNING 0x0040
-#define SDHCI_CTRL_TUNED_CLK 0x80
#define SDHCI_TUNING_LOOP_COUNT 40
static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
@@ -190,30 +185,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
}
if (mmc->selected_mode > SD_HS &&
- mmc->selected_mode <= UHS_DDR50) {
- reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
- reg &= ~SDHCI_CTRL2_MODE_MASK;
- switch (mmc->selected_mode) {
- case UHS_SDR12:
- reg |= UHS_SDR12_BUS_SPEED;
- break;
- case UHS_SDR25:
- reg |= UHS_SDR25_BUS_SPEED;
- break;
- case UHS_SDR50:
- reg |= UHS_SDR50_BUS_SPEED;
- break;
- case UHS_SDR104:
- reg |= UHS_SDR104_BUS_SPEED;
- break;
- case UHS_DDR50:
- reg |= UHS_DDR50_BUS_SPEED;
- break;
- default:
- break;
- }
- sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
- }
+ mmc->selected_mode <= UHS_DDR50)
+ sdhci_set_uhs_timing(host);
}
#endif
diff --git a/include/sdhci.h b/include/sdhci.h
index 3dcbc14965..01addb7a60 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -144,7 +144,23 @@
#define SDHCI_ACMD12_ERR 0x3C
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2 0x3E
+#define SDHCI_CTRL_UHS_MASK 0x0007
+#define SDHCI_CTRL_UHS_SDR12 0x0000
+#define SDHCI_CTRL_UHS_SDR25 0x0001
+#define SDHCI_CTRL_UHS_SDR50 0x0002
+#define SDHCI_CTRL_UHS_SDR104 0x0003
+#define SDHCI_CTRL_UHS_DDR50 0x0004
+#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
+#define SDHCI_CTRL_DRV_TYPE_B 0x0000
+#define SDHCI_CTRL_DRV_TYPE_A 0x0010
+#define SDHCI_CTRL_DRV_TYPE_C 0x0020
+#define SDHCI_CTRL_DRV_TYPE_D 0x0030
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
@@ -467,6 +483,7 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
#endif /* !CONFIG_BLK */
+void sdhci_set_uhs_timing(struct sdhci_host *host);
#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
--
2.17.1
next prev parent reply other threads:[~2019-05-23 17:37 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-23 17:37 [U-Boot] [PATCH v4 00/15] Add Support for eMMC in AM65x-evm Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 01/15] arm64: dts: k3: Sync sdhci0 node from kernel and change driver name Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 02/15] mmc: am654_sdhci: Remove quirks Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 03/15] regmap: Add API regmap_init_mem_index() Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 04/15] mmc: sdhci: Add support for sdhci-caps-mask Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 05/15] mmc: sdhci: Make sdhci_set_clock() non static Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 06/15] arm: dts: k3: Add phy specific properties to SD card node Faiz Abbas
2019-05-23 18:57 ` Andreas Dannenberg
2019-05-29 9:47 ` Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 07/15] mmc: sdhci: Make set_ios_post() return int Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 08/15] mmc: am654_sdhci: Add Support for PHY Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 09/15] configs: am65x_evm: Enable CONFIG_REGMAP Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 10/15] mmc: am654_sdhci: Use f_max in mmc_config Faiz Abbas
2019-05-23 17:37 ` Faiz Abbas [this message]
2019-05-23 17:37 ` [U-Boot] [PATCH v4 12/15] mmc: am654_sdhci: Add a platform specific set_control_reg() callback Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 13/15] configs: am65x: Add configs to support environment in eMMC Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 14/15] am65x_evm: Add Support for creating a filesystem GPT partition " Faiz Abbas
2019-05-23 17:37 ` [U-Boot] [PATCH v4 15/15] configs: am65x_evm_a53: Add Support for creating GPT partitions Faiz Abbas
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