From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97034C282DD for ; Thu, 23 May 2019 20:51:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D9742075B for ; Thu, 23 May 2019 20:51:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="bu0Q70BF"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="i94FTHJC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387894AbfEWUv4 (ORCPT ); Thu, 23 May 2019 16:51:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49554 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387885AbfEWUv4 (ORCPT ); Thu, 23 May 2019 16:51:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EA19C60E42; Thu, 23 May 2019 20:51:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1558644714; bh=YV+gAwwbS79U/5jkzKimUPb7BPvziSeuL9ft4ZBfyp0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bu0Q70BFcoTXFzp3Ph2zeeZYZ+3Bs4QKUWUag/BIw0krkQw5oVkdsefOszz0JoC2m +6rJSt63tWZM9gqobqD490vsaTSfdush1oQjjrTacZf6aj+O5JMOfPGKEkQZCcxciC +tMILimbic9eWWk6leoXwr79GGSrS4XmSbhnVLzk= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5900F6030E; Thu, 23 May 2019 20:51:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1558644713; bh=YV+gAwwbS79U/5jkzKimUPb7BPvziSeuL9ft4ZBfyp0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=i94FTHJC6TLAb3YTlqRnWIXo3Ry0FDQLxkcXoeNT4N+h1BzSNHJVvNhmNIiUjlqUs GrtSl3Q7RgGvsYN98j+fLtDL8K3GSUwL95uoRUuupS9FJkwTUThlB00jEvjqVnCJaX fkgSFtOBgjRD9xn2n1SPfijhMsHFguwdL+9B9VCo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5900F6030E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Thu, 23 May 2019 14:51:51 -0600 From: Jordan Crouse To: Sean Paul Cc: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Sean Paul , Rob Clark , linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2 4/6] drm/msm/a6xx: Remove devm calls from gmu driver Message-ID: <20190523205151.GE18360@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Sean Paul , Rob Clark , linux-arm-msm@vger.kernel.org References: <20190523171653.138678-1-sean@poorly.run> <20190523171653.138678-4-sean@poorly.run> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190523171653.138678-4-sean@poorly.run> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, May 23, 2019 at 01:16:43PM -0400, Sean Paul wrote: > From: Sean Paul > > The gmu driver is initialized and cleaned up with calls from the gpu driver. As > such, the platform device stays valid after a6xx_gmu_remove is called and the > device managed resources are not freed. In the case of gpu probe failures or > unbind, these resources will remain managed. > > If the gpu bind is run again (eg: if there's a probe defer somewhere in msm), > these resources will be initialized again for the same device, creating multiple > references. In the case of irqs, this causes failures since the irqs are > not shared (nor should they be). > > This patch removes all devm_* calls and manually cleans things up in > gmu_remove. > > Changes in v2: > - Add iounmap and free_irq to gmu_probe error paths > > Cc: Jordan Crouse > Signed-off-by: Sean Paul As we discussed in IRC, I feel like the way we are probing and dealing with the GMU device is messing up the reference counting. I had hoped that a put_device() would do the trick but testing showed it didn't so there is clearly remaining fail that we should eventually find and fix. That said; there is really no reason to be using managed resources for this device so this is an entirely appropriate patch. Reviewed-by: Jordan Crouse > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 33 ++++++++++++++++++--------- > 1 file changed, 22 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 7465423e9b71..f7240c9e11fb 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -505,9 +505,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > > err: > if (!IS_ERR_OR_NULL(pdcptr)) > - devm_iounmap(gmu->dev, pdcptr); > + iounmap(pdcptr); > if (!IS_ERR_OR_NULL(seqptr)) > - devm_iounmap(gmu->dev, seqptr); > + iounmap(seqptr); > } > > /* > @@ -1197,7 +1197,7 @@ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, > return ERR_PTR(-EINVAL); > } > > - ret = devm_ioremap(&pdev->dev, res->start, resource_size(res)); > + ret = ioremap(res->start, resource_size(res)); > if (!ret) { > DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); > return ERR_PTR(-EINVAL); > @@ -1213,10 +1213,10 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, > > irq = platform_get_irq_byname(pdev, name); > > - ret = devm_request_irq(&pdev->dev, irq, handler, IRQF_TRIGGER_HIGH, > - name, gmu); > + ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); > if (ret) { > - DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s\n", name); > + DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", > + name, ret); > return ret; > } > > @@ -1241,12 +1241,18 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) > dev_pm_domain_detach(gmu->gxpd, false); > } > > + iounmap(gmu->mmio); > + gmu->mmio = NULL; > + > a6xx_gmu_memory_free(gmu, gmu->hfi); > > iommu_detach_device(gmu->domain, gmu->dev); > > iommu_domain_free(gmu->domain); > > + free_irq(gmu->gmu_irq, gmu); > + free_irq(gmu->hfi_irq, gmu); > + > gmu->initialized = false; > } > > @@ -1281,24 +1287,24 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > /* Allocate memory for for the HFI queues */ > gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); > if (IS_ERR(gmu->hfi)) > - goto err; > + goto err_memory; > > /* Allocate memory for the GMU debug region */ > gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); > if (IS_ERR(gmu->debug)) > - goto err; > + goto err_memory; > > /* Map the GMU registers */ > gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); > if (IS_ERR(gmu->mmio)) > - goto err; > + goto err_memory; > > /* Get the HFI and GMU interrupts */ > gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); > gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); > > if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) > - goto err; > + goto err_mmio; > > /* > * Get a link to the GX power domain to reset the GPU in case of GMU > @@ -1315,7 +1321,12 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > gmu->initialized = true; > > return 0; > -err: > + > +err_mmio: > + iounmap(gmu->mmio); > + free_irq(gmu->gmu_irq, gmu); > + free_irq(gmu->hfi_irq, gmu); > +err_memory: > a6xx_gmu_memory_free(gmu, gmu->hfi); > > if (gmu->domain) { > -- > Sean Paul, Software Engineer, Google / Chromium OS > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: Re: [PATCH v2 4/6] drm/msm/a6xx: Remove devm calls from gmu driver Date: Thu, 23 May 2019 14:51:51 -0600 Message-ID: <20190523205151.GE18360@jcrouse1-lnx.qualcomm.com> References: <20190523171653.138678-1-sean@poorly.run> <20190523171653.138678-4-sean@poorly.run> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20190523171653.138678-4-sean-p7yTbzM4H96eqtR555YLDQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: Sean Paul Cc: Sean Paul , Rob Clark , freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBNYXkgMjMsIDIwMTkgYXQgMDE6MTY6NDNQTSAtMDQwMCwgU2VhbiBQYXVsIHdyb3Rl Ogo+IEZyb206IFNlYW4gUGF1bCA8c2VhbnBhdWxAY2hyb21pdW0ub3JnPgo+IAo+IFRoZSBnbXUg ZHJpdmVyIGlzIGluaXRpYWxpemVkIGFuZCBjbGVhbmVkIHVwIHdpdGggY2FsbHMgZnJvbSB0aGUg Z3B1IGRyaXZlci4gQXMKPiBzdWNoLCB0aGUgcGxhdGZvcm0gZGV2aWNlIHN0YXlzIHZhbGlkIGFm dGVyIGE2eHhfZ211X3JlbW92ZSBpcyBjYWxsZWQgYW5kIHRoZQo+IGRldmljZSBtYW5hZ2VkIHJl c291cmNlcyBhcmUgbm90IGZyZWVkLiBJbiB0aGUgY2FzZSBvZiBncHUgcHJvYmUgZmFpbHVyZXMg b3IKPiB1bmJpbmQsIHRoZXNlIHJlc291cmNlcyB3aWxsIHJlbWFpbiBtYW5hZ2VkLgo+IAo+IElm IHRoZSBncHUgYmluZCBpcyBydW4gYWdhaW4gKGVnOiBpZiB0aGVyZSdzIGEgcHJvYmUgZGVmZXIg c29tZXdoZXJlIGluIG1zbSksCj4gdGhlc2UgcmVzb3VyY2VzIHdpbGwgYmUgaW5pdGlhbGl6ZWQg YWdhaW4gZm9yIHRoZSBzYW1lIGRldmljZSwgY3JlYXRpbmcgbXVsdGlwbGUKPiByZWZlcmVuY2Vz LiBJbiB0aGUgY2FzZSBvZiBpcnFzLCB0aGlzIGNhdXNlcyBmYWlsdXJlcyBzaW5jZSB0aGUgaXJx cyBhcmUKPiBub3Qgc2hhcmVkIChub3Igc2hvdWxkIHRoZXkgYmUpLgo+IAo+IFRoaXMgcGF0Y2gg cmVtb3ZlcyBhbGwgZGV2bV8qIGNhbGxzIGFuZCBtYW51YWxseSBjbGVhbnMgdGhpbmdzIHVwIGlu Cj4gZ211X3JlbW92ZS4KPiAKPiBDaGFuZ2VzIGluIHYyOgo+IC0gQWRkIGlvdW5tYXAgYW5kIGZy ZWVfaXJxIHRvIGdtdV9wcm9iZSBlcnJvciBwYXRocwo+IAo+IENjOiBKb3JkYW4gQ3JvdXNlIDxq Y3JvdXNlQGNvZGVhdXJvcmEub3JnPgo+IFNpZ25lZC1vZmYtYnk6IFNlYW4gUGF1bCA8c2VhbnBh dWxAY2hyb21pdW0ub3JnPgoKQXMgd2UgZGlzY3Vzc2VkIGluIElSQywgSSBmZWVsIGxpa2UgdGhl IHdheSB3ZSBhcmUgcHJvYmluZyBhbmQgZGVhbGluZyB3aXRoCnRoZSBHTVUgZGV2aWNlIGlzIG1l c3NpbmcgdXAgdGhlIHJlZmVyZW5jZSBjb3VudGluZy4gSSBoYWQgaG9wZWQgdGhhdCBhCnB1dF9k ZXZpY2UoKSB3b3VsZCBkbyB0aGUgdHJpY2sgYnV0IHRlc3Rpbmcgc2hvd2VkIGl0IGRpZG4ndCBz byB0aGVyZSBpcyBjbGVhcmx5CnJlbWFpbmluZyBmYWlsIHRoYXQgd2Ugc2hvdWxkIGV2ZW50dWFs bHkgZmluZCBhbmQgZml4LgoKVGhhdCBzYWlkOyB0aGVyZSBpcyByZWFsbHkgbm8gcmVhc29uIHRv IGJlIHVzaW5nIG1hbmFnZWQgcmVzb3VyY2VzIGZvciB0aGlzCmRldmljZSBzbyB0aGlzIGlzIGFu IGVudGlyZWx5IGFwcHJvcHJpYXRlIHBhdGNoLgoKUmV2aWV3ZWQtYnk6IEpvcmRhbiBDcm91c2Ug PGpjcm91c2VAY29kZWF1cm9yYS5vcmc+Cgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vbXNtL2Fk cmVuby9hNnh4X2dtdS5jIHwgMzMgKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tCj4gIDEgZmls ZSBjaGFuZ2VkLCAyMiBpbnNlcnRpb25zKCspLCAxMSBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8vYTZ4eF9nbXUuYyBiL2RyaXZlcnMvZ3B1 L2RybS9tc20vYWRyZW5vL2E2eHhfZ211LmMKPiBpbmRleCA3NDY1NDIzZTliNzEuLmY3MjQwYzll MTFmYiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbXNtL2FkcmVuby9hNnh4X2dtdS5j Cj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9hZHJlbm8vYTZ4eF9nbXUuYwo+IEBAIC01MDUs OSArNTA1LDkgQEAgc3RhdGljIHZvaWQgYTZ4eF9nbXVfcnBtaF9pbml0KHN0cnVjdCBhNnh4X2dt dSAqZ211KQo+ICAKPiAgZXJyOgo+ICAJaWYgKCFJU19FUlJfT1JfTlVMTChwZGNwdHIpKQo+IC0J CWRldm1faW91bm1hcChnbXUtPmRldiwgcGRjcHRyKTsKPiArCQlpb3VubWFwKHBkY3B0cik7Cj4g IAlpZiAoIUlTX0VSUl9PUl9OVUxMKHNlcXB0cikpCj4gLQkJZGV2bV9pb3VubWFwKGdtdS0+ZGV2 LCBzZXFwdHIpOwo+ICsJCWlvdW5tYXAoc2VxcHRyKTsKPiAgfQo+ICAKPiAgLyoKPiBAQCAtMTE5 Nyw3ICsxMTk3LDcgQEAgc3RhdGljIHZvaWQgX19pb21lbSAqYTZ4eF9nbXVfZ2V0X21taW8oc3Ry dWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiwKPiAgCQlyZXR1cm4gRVJSX1BUUigtRUlOVkFMKTsK PiAgCX0KPiAgCj4gLQlyZXQgPSBkZXZtX2lvcmVtYXAoJnBkZXYtPmRldiwgcmVzLT5zdGFydCwg cmVzb3VyY2Vfc2l6ZShyZXMpKTsKPiArCXJldCA9IGlvcmVtYXAocmVzLT5zdGFydCwgcmVzb3Vy Y2Vfc2l6ZShyZXMpKTsKPiAgCWlmICghcmV0KSB7Cj4gIAkJRFJNX0RFVl9FUlJPUigmcGRldi0+ ZGV2LCAiVW5hYmxlIHRvIG1hcCB0aGUgJXMgcmVnaXN0ZXJzXG4iLCBuYW1lKTsKPiAgCQlyZXR1 cm4gRVJSX1BUUigtRUlOVkFMKTsKPiBAQCAtMTIxMywxMCArMTIxMywxMCBAQCBzdGF0aWMgaW50 IGE2eHhfZ211X2dldF9pcnEoc3RydWN0IGE2eHhfZ211ICpnbXUsIHN0cnVjdCBwbGF0Zm9ybV9k ZXZpY2UgKnBkZXYsCj4gIAo+ICAJaXJxID0gcGxhdGZvcm1fZ2V0X2lycV9ieW5hbWUocGRldiwg bmFtZSk7Cj4gIAo+IC0JcmV0ID0gZGV2bV9yZXF1ZXN0X2lycSgmcGRldi0+ZGV2LCBpcnEsIGhh bmRsZXIsIElSUUZfVFJJR0dFUl9ISUdILAo+IC0JCW5hbWUsIGdtdSk7Cj4gKwlyZXQgPSByZXF1 ZXN0X2lycShpcnEsIGhhbmRsZXIsIElSUUZfVFJJR0dFUl9ISUdILCBuYW1lLCBnbXUpOwo+ICAJ aWYgKHJldCkgewo+IC0JCURSTV9ERVZfRVJST1IoJnBkZXYtPmRldiwgIlVuYWJsZSB0byBnZXQg aW50ZXJydXB0ICVzXG4iLCBuYW1lKTsKPiArCQlEUk1fREVWX0VSUk9SKCZwZGV2LT5kZXYsICJV bmFibGUgdG8gZ2V0IGludGVycnVwdCAlcyAlZFxuIiwKPiArCQkJICAgICAgbmFtZSwgcmV0KTsK PiAgCQlyZXR1cm4gcmV0Owo+ICAJfQo+ICAKPiBAQCAtMTI0MSwxMiArMTI0MSwxOCBAQCB2b2lk IGE2eHhfZ211X3JlbW92ZShzdHJ1Y3QgYTZ4eF9ncHUgKmE2eHhfZ3B1KQo+ICAJCWRldl9wbV9k b21haW5fZGV0YWNoKGdtdS0+Z3hwZCwgZmFsc2UpOwo+ICAJfQo+ICAKPiArCWlvdW5tYXAoZ211 LT5tbWlvKTsKPiArCWdtdS0+bW1pbyA9IE5VTEw7Cj4gKwo+ICAJYTZ4eF9nbXVfbWVtb3J5X2Zy ZWUoZ211LCBnbXUtPmhmaSk7Cj4gIAo+ICAJaW9tbXVfZGV0YWNoX2RldmljZShnbXUtPmRvbWFp biwgZ211LT5kZXYpOwo+ICAKPiAgCWlvbW11X2RvbWFpbl9mcmVlKGdtdS0+ZG9tYWluKTsKPiAg Cj4gKwlmcmVlX2lycShnbXUtPmdtdV9pcnEsIGdtdSk7Cj4gKwlmcmVlX2lycShnbXUtPmhmaV9p cnEsIGdtdSk7Cj4gKwo+ICAJZ211LT5pbml0aWFsaXplZCA9IGZhbHNlOwo+ICB9Cj4gIAo+IEBA IC0xMjgxLDI0ICsxMjg3LDI0IEBAIGludCBhNnh4X2dtdV9wcm9iZShzdHJ1Y3QgYTZ4eF9ncHUg KmE2eHhfZ3B1LCBzdHJ1Y3QgZGV2aWNlX25vZGUgKm5vZGUpCj4gIAkvKiBBbGxvY2F0ZSBtZW1v cnkgZm9yIGZvciB0aGUgSEZJIHF1ZXVlcyAqLwo+ICAJZ211LT5oZmkgPSBhNnh4X2dtdV9tZW1v cnlfYWxsb2MoZ211LCBTWl8xNkspOwo+ICAJaWYgKElTX0VSUihnbXUtPmhmaSkpCj4gLQkJZ290 byBlcnI7Cj4gKwkJZ290byBlcnJfbWVtb3J5Owo+ICAKPiAgCS8qIEFsbG9jYXRlIG1lbW9yeSBm b3IgdGhlIEdNVSBkZWJ1ZyByZWdpb24gKi8KPiAgCWdtdS0+ZGVidWcgPSBhNnh4X2dtdV9tZW1v cnlfYWxsb2MoZ211LCBTWl8xNkspOwo+ICAJaWYgKElTX0VSUihnbXUtPmRlYnVnKSkKPiAtCQln b3RvIGVycjsKPiArCQlnb3RvIGVycl9tZW1vcnk7Cj4gIAo+ICAJLyogTWFwIHRoZSBHTVUgcmVn aXN0ZXJzICovCj4gIAlnbXUtPm1taW8gPSBhNnh4X2dtdV9nZXRfbW1pbyhwZGV2LCAiZ211Iik7 Cj4gIAlpZiAoSVNfRVJSKGdtdS0+bW1pbykpCj4gLQkJZ290byBlcnI7Cj4gKwkJZ290byBlcnJf bWVtb3J5Owo+ICAKPiAgCS8qIEdldCB0aGUgSEZJIGFuZCBHTVUgaW50ZXJydXB0cyAqLwo+ICAJ Z211LT5oZmlfaXJxID0gYTZ4eF9nbXVfZ2V0X2lycShnbXUsIHBkZXYsICJoZmkiLCBhNnh4X2hm aV9pcnEpOwo+ICAJZ211LT5nbXVfaXJxID0gYTZ4eF9nbXVfZ2V0X2lycShnbXUsIHBkZXYsICJn bXUiLCBhNnh4X2dtdV9pcnEpOwo+ICAKPiAgCWlmIChnbXUtPmhmaV9pcnEgPCAwIHx8IGdtdS0+ Z211X2lycSA8IDApCj4gLQkJZ290byBlcnI7Cj4gKwkJZ290byBlcnJfbW1pbzsKPiAgCj4gIAkv Kgo+ICAJICogR2V0IGEgbGluayB0byB0aGUgR1ggcG93ZXIgZG9tYWluIHRvIHJlc2V0IHRoZSBH UFUgaW4gY2FzZSBvZiBHTVUKPiBAQCAtMTMxNSw3ICsxMzIxLDEyIEBAIGludCBhNnh4X2dtdV9w cm9iZShzdHJ1Y3QgYTZ4eF9ncHUgKmE2eHhfZ3B1LCBzdHJ1Y3QgZGV2aWNlX25vZGUgKm5vZGUp Cj4gIAlnbXUtPmluaXRpYWxpemVkID0gdHJ1ZTsKPiAgCj4gIAlyZXR1cm4gMDsKPiAtZXJyOgo+ ICsKPiArZXJyX21taW86Cj4gKwlpb3VubWFwKGdtdS0+bW1pbyk7Cj4gKwlmcmVlX2lycShnbXUt PmdtdV9pcnEsIGdtdSk7Cj4gKwlmcmVlX2lycShnbXUtPmhmaV9pcnEsIGdtdSk7Cj4gK2Vycl9t ZW1vcnk6Cj4gIAlhNnh4X2dtdV9tZW1vcnlfZnJlZShnbXUsIGdtdS0+aGZpKTsKPiAgCj4gIAlp ZiAoZ211LT5kb21haW4pIHsKPiAtLSAKPiBTZWFuIFBhdWwsIFNvZnR3YXJlIEVuZ2luZWVyLCBH b29nbGUgLyBDaHJvbWl1bSBPUwo+IAoKLS0gClRoZSBRdWFsY29tbSBJbm5vdmF0aW9uIENlbnRl ciwgSW5jLiBpcyBhIG1lbWJlciBvZiBDb2RlIEF1cm9yYSBGb3J1bSwKYSBMaW51eCBGb3VuZGF0 aW9uIENvbGxhYm9yYXRpdmUgUHJvamVjdApfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpGcmVlZHJlbm8gbWFpbGluZyBsaXN0CkZyZWVkcmVub0BsaXN0cy5m cmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0 aW5mby9mcmVlZHJlbm8=