[U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static

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* [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static
@ 2019-05-24 13:40 Luca Ceresoli
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files Luca Ceresoli
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Luca Ceresoli @ 2019-05-24 13:40 UTC (permalink / raw)
  To: u-boot

Fixes sparse warnings when building zynqmp defconfigs:
  ./board/xilinx/zynqmp/xil_io.h:12:6: warning: symbol 'Xil_Out32' was not declared. Should it be static?
  ./board/xilinx/zynqmp/xil_io.h:17:5: warning: symbol 'Xil_In32' was not declared. Should it be static?
  ./board/xilinx/zynqmp/xil_io.h:22:6: warning: symbol 'usleep' was not declared. Should it be static?

Also add __maybe_unused to usleep() since it is not used by minimized
psu_init_gpl.c files, so it would warn as "defined but not used".

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>

---

Chages v1 -> v2:
 - fix commit text (Michal)
---
 board/xilinx/zynqmp/xil_io.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index c476c902ebcb..1c1bf32adaae 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -9,17 +9,17 @@
 
 #define xil_printf(...)
 
-void Xil_Out32(unsigned long addr, unsigned long val)
+static void Xil_Out32(unsigned long addr, unsigned long val)
 {
 	writel(val, addr);
 }
 
-int Xil_In32(unsigned long addr)
+static int Xil_In32(unsigned long addr)
 {
 	return readl(addr);
 }
 
-void usleep(u32 sleep)
+static void __maybe_unused usleep(u32 sleep)
 {
 	udelay(sleep);
 }
-- 
2.21.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files
  2019-05-24 13:40 [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Luca Ceresoli
@ 2019-05-24 13:40 ` Luca Ceresoli
  2019-05-28  6:29   ` Michal Simek
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit Luca Ceresoli
  2019-05-28  6:29 ` [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Michal Simek
  2 siblings, 1 reply; 7+ messages in thread
From: Luca Ceresoli @ 2019-05-24 13:40 UTC (permalink / raw)
  To: u-boot

This script transforms a pair of psu_init_gpl.c and .h files produced by
the Xilinx Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that
is almost checkpatch compliant.

Based on a script by Michal Simek.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>

---

Changes v1 -> v2:
 - document that is INPUT_DIR==OUTPUT_DIR then psu_init_gpl.c is overwritten
 - minor improvement to commit message
 - show help text if script is called without parameters (Michal)
---
 tools/zynqmp_psu_init_minimize.sh | 145 ++++++++++++++++++++++++++++++
 1 file changed, 145 insertions(+)
 create mode 100755 tools/zynqmp_psu_init_minimize.sh

diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh
new file mode 100755
index 000000000000..b0a07f9080a6
--- /dev/null
+++ b/tools/zynqmp_psu_init_minimize.sh
@@ -0,0 +1,145 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
+# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
+
+usage()
+{
+    cat <<EOF
+
+Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx
+Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost
+checkpatch compliant. Minor coding style might still be needed. Must be
+run from the top-level U-Boot source directory.
+
+Usage:   zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR
+Example: zynqmp_psu_init_minimize.sh \\
+                 /path/to/original/psu_init_gpl_c_and_h/ \\
+                 board/xilinx/zynqmp/<my_board>/
+
+Notes:   INPUT_DIR must contain both .c and .h files.
+         If INPUT_DIR and OUTPUT_DIR are the same directory,
+         psu_init_gpl.c will be overwritten.
+
+EOF
+}
+
+set -o errexit -o errtrace
+set -o nounset
+
+if [ $# -ne 2 ]
+then
+    usage >&2
+    exit 1
+fi
+
+IN="${1}/psu_init_gpl.c"
+OUT="${2}/psu_init_gpl.c"
+TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX)
+trap "rm ${TMP}" ERR
+
+# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT
+sed -e '/sleep.h/d' \
+    -e '/xil_io.h/d' \
+    ${IN} >${TMP}
+cp ${TMP} ${OUT}
+
+# preprocess to expand defines, then remove cpp lines starting with '#'
+gcc -I${1} -E ${OUT} -o ${TMP}
+sed '/^#/d' ${TMP} >${OUT}
+
+# Remove trivial code before psu_pll_init_data()
+sed -ni '/psu_pll_init_data/,$p' ${OUT}
+
+# Functions are lowercase in U-Boot, rename them
+sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT}
+sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT}
+sed -i 's/RegValue/regvalue/g' ${OUT}
+sed -i 's/MaskStatus/maskstatus/g' ${OUT}
+
+sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT}
+
+FUNCS_TO_REMOVE="psu_protection
+psu_..._protection
+psu_init_xppu_aper_ram
+mask_delay(u32
+mask_read(u32
+dpll_prog
+mask_poll(u32
+mask_pollonvalue(u32
+psu_ps_pl_reset_config_data
+psu_ps_pl_isolation_removal_data
+psu_apply_master_tz
+psu_post_config_data
+psu_post_config_data
+psu_peripherals_powerdwn_data
+psu_init_ddr_self_refresh
+xmpu
+xppu
+"
+for i in $FUNCS_TO_REMOVE; do
+sed -i "/$i/,/^}$/d" ${OUT}
+done
+
+scripts/Lindent ${OUT}
+
+# Prepend 'static' to internal functions
+sed -i 's/^.*data(void)$/static &/g' ${OUT}
+sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT}
+sed -i 's/^void init_peripheral/static &/g' ${OUT}
+sed -i 's/^int serdes/static &/g' ${OUT}
+sed -i 's/^int init_serdes/static &/g' ${OUT}
+sed -i 's/^unsigned long /static &/g' ${OUT}
+
+sed -i 's/()$/(void)/g' ${OUT}
+sed -i 's/0X/0x/g' ${OUT}
+
+# Add header
+cat << EOF >${TMP}
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+EOF
+
+cat ${OUT} >>${TMP}
+cp ${TMP} ${OUT}
+
+# Temporarily convert newlines to do some mangling across lines
+tr "\n" "\r" <${OUT} >${TMP}
+
+# Cleanup empty loops. E.g.:
+# |while (e) {|
+# |           | ==> |while (e)|
+# |    }      |     |    ;    |
+# |           |
+sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP}
+
+# Remove empty line between variable declaration
+sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP}
+
+# Remove empty lines at function beginning/end
+sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP}
+sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP}
+
+# Remove empty lines after '{' line
+sed -i -e 's| {\r\r| {\r|g' ${TMP}
+
+# Remove braces {} around single statement blocks. E.g.:
+# | while (e) { |    | while (e) |
+# |     stg();  | => |     stg();|
+# | }           |
+sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP}
+
+# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.:
+# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...)
+sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP}
+
+# Convert back newlines
+tr "\r" "\n" <${TMP} >${OUT}
+
+rm ${TMP}
-- 
2.21.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit
  2019-05-24 13:40 [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Luca Ceresoli
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files Luca Ceresoli
@ 2019-05-24 13:40 ` Luca Ceresoli
  2019-05-28  7:45   ` Michal Simek
  2019-05-28  6:29 ` [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Michal Simek
  2 siblings, 1 reply; 7+ messages in thread
From: Luca Ceresoli @ 2019-05-24 13:40 UTC (permalink / raw)
  To: u-boot

Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.

The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and then minimized by
tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
it is not mentioned in device tree and fixed a checkpatch error.

[0] https://github.com/Avnet/bdf/tree/3686c9ff7d2f0467fb4fcf39f861b8d6ff183b12/ultrazed_7ev_cc/1.1

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>

---

Changes v1 -> v2:
 - remove serdes code from psu_init_gpl.c since no serdes is enabled in DT
   (Michal)
 - split DT in two files: SOM and carrier card (Michal)
 - improved DT comments, added product URLs
 - DT: add missing phy-handle under ethernet node (Michal)

Whole patchset tested on:
 - current u-boot/master, as is
 - current u-boot-microblaze/master
 - current u-boot-microblaze/master with the addtion of
   commit f89d6133eef2 ("configs: move CONFIG_SPL_TEXT_BASE to Kconfig")
---
 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/avnet-ultrazedev-cc.dts          |  58 ++
 arch/arm/dts/avnet-ultrazedev-som.dtsi        |  54 ++
 .../zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c | 663 ++++++++++++++++++
 configs/avnet_ultrazedev_defconfig            |  64 ++
 5 files changed, 840 insertions(+)
 create mode 100644 arch/arm/dts/avnet-ultrazedev-cc.dts
 create mode 100644 arch/arm/dts/avnet-ultrazedev-som.dtsi
 create mode 100644 board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
 create mode 100644 configs/avnet_ultrazedev_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8167cdb4e856..d82dc6529749 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zybo-z7.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	avnet-ultra96-rev1.dtb			\
+	avnet-ultrazedev-cc.dtb			\
 	zynqmp-mini.dtb				\
 	zynqmp-mini-emmc0.dtb			\
 	zynqmp-mini-emmc1.dtb			\
diff --git a/arch/arm/dts/avnet-ultrazedev-cc.dts b/arch/arm/dts/avnet-ultrazedev-cc.dts
new file mode 100644
index 000000000000..d94dd4246f7b
--- /dev/null
+++ b/arch/arm/dts/avnet-ultrazedev-cc.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV Carrier Card (based on the UltraZed-EV SoM)
+ * http://ultrazed.org/product/ultrazed-ev-carrier-card
+ */
+
+/dts-v1/;
+
+#include "avnet-ultrazedev-som.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = &eeprom;
+	};
+	aliases {
+		ethernet0 = &gem3;
+		serial0 = &uart0;
+	};
+};
+
+&uart0 {
+	device_type = "serial";
+	port-number = <0>;
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&i2c_cc {
+	/* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
+	eeprom: eeprom at 51 {
+		compatible = "at,24c02", "i2c-eeprom";
+		reg = <0x51>;
+	};
+
+	/* IDT Versa Clock 5P49V5935B */
+	vc5: clock-generator at 6a {
+		compatible = "idt,5p49v5935";
+		reg = <0x6a>;
+		#clock-cells = <1>;
+	};
+};
+
+/* Ethernet RJ-45 */
+&gem3 {
+	status = "okay";
+};
+
+/* microSD card slot */
+&sdhci1 {
+	status = "okay";
+	xlnx,mio_bank = <1>;
+	clock-frequency = <199998000>;
+	max-frequency = <50000000>;
+	no-1-8-v;
+	disable-wp;
+};
diff --git a/arch/arm/dts/avnet-ultrazedev-som.dtsi b/arch/arm/dts/avnet-ultrazedev-som.dtsi
new file mode 100644
index 000000000000..4ce0a2d31786
--- /dev/null
+++ b/arch/arm/dts/avnet-ultrazedev-som.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV SoM
+ * http://ultrazed.org/product/ultrazed-ev
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
+		      <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	i2cswitch at 70 {
+		compatible = "nxp,pca9543";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		/* I2C connected to Carrier Card via JX3A1/JX3C1 */
+		i2c_cc: i2c at 0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
+&gem3 {
+	phy-mode = "rgmii-id";
+	phy-handle = <&gem3phy>;
+	gem3phy: phy at 0 {
+		reg = <0x0>;
+	};
+};
+
+/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
+&sdhci0 {
+	status = "okay";
+	xlnx,mio_bank = <0>;
+	clock-frequency = <199998000>;
+};
diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
new file mode 100644
index 000000000000..68dcd2d2af9e
--- /dev/null
+++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return (0);
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return (0);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/configs/avnet_ultrazedev_defconfig b/configs/avnet_ultrazedev_defconfig
new file mode 100644
index 000000000000..6da8283aef9f
--- /dev/null
+++ b/configs/avnet_ultrazedev_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
2.21.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static
  2019-05-24 13:40 [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Luca Ceresoli
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files Luca Ceresoli
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit Luca Ceresoli
@ 2019-05-28  6:29 ` Michal Simek
  2 siblings, 0 replies; 7+ messages in thread
From: Michal Simek @ 2019-05-28  6:29 UTC (permalink / raw)
  To: u-boot

On 24. 05. 19 15:40, Luca Ceresoli wrote:
> Fixes sparse warnings when building zynqmp defconfigs:
>   ./board/xilinx/zynqmp/xil_io.h:12:6: warning: symbol 'Xil_Out32' was not declared. Should it be static?
>   ./board/xilinx/zynqmp/xil_io.h:17:5: warning: symbol 'Xil_In32' was not declared. Should it be static?
>   ./board/xilinx/zynqmp/xil_io.h:22:6: warning: symbol 'usleep' was not declared. Should it be static?
> 
> Also add __maybe_unused to usleep() since it is not used by minimized
> psu_init_gpl.c files, so it would warn as "defined but not used".
> 
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> 
> ---
> 
> Chages v1 -> v2:
>  - fix commit text (Michal)
> ---
>  board/xilinx/zynqmp/xil_io.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
> index c476c902ebcb..1c1bf32adaae 100644
> --- a/board/xilinx/zynqmp/xil_io.h
> +++ b/board/xilinx/zynqmp/xil_io.h
> @@ -9,17 +9,17 @@
>  
>  #define xil_printf(...)
>  
> -void Xil_Out32(unsigned long addr, unsigned long val)
> +static void Xil_Out32(unsigned long addr, unsigned long val)
>  {
>  	writel(val, addr);
>  }
>  
> -int Xil_In32(unsigned long addr)
> +static int Xil_In32(unsigned long addr)
>  {
>  	return readl(addr);
>  }
>  
> -void usleep(u32 sleep)
> +static void __maybe_unused usleep(u32 sleep)
>  {
>  	udelay(sleep);
>  }
> 

applied.
M

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files Luca Ceresoli
@ 2019-05-28  6:29   ` Michal Simek
  0 siblings, 0 replies; 7+ messages in thread
From: Michal Simek @ 2019-05-28  6:29 UTC (permalink / raw)
  To: u-boot

On 24. 05. 19 15:40, Luca Ceresoli wrote:
> This script transforms a pair of psu_init_gpl.c and .h files produced by
> the Xilinx Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that
> is almost checkpatch compliant.
> 
> Based on a script by Michal Simek.
> 
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> 
> ---
> 
> Changes v1 -> v2:
>  - document that is INPUT_DIR==OUTPUT_DIR then psu_init_gpl.c is overwritten
>  - minor improvement to commit message
>  - show help text if script is called without parameters (Michal)
> ---
>  tools/zynqmp_psu_init_minimize.sh | 145 ++++++++++++++++++++++++++++++
>  1 file changed, 145 insertions(+)
>  create mode 100755 tools/zynqmp_psu_init_minimize.sh
> 
> diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh
> new file mode 100755
> index 000000000000..b0a07f9080a6
> --- /dev/null
> +++ b/tools/zynqmp_psu_init_minimize.sh
> @@ -0,0 +1,145 @@
> +#!/bin/bash
> +# SPDX-License-Identifier: GPL-2.0+
> +# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
> +# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
> +
> +usage()
> +{
> +    cat <<EOF
> +
> +Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx
> +Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost
> +checkpatch compliant. Minor coding style might still be needed. Must be
> +run from the top-level U-Boot source directory.
> +
> +Usage:   zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR
> +Example: zynqmp_psu_init_minimize.sh \\
> +                 /path/to/original/psu_init_gpl_c_and_h/ \\
> +                 board/xilinx/zynqmp/<my_board>/
> +
> +Notes:   INPUT_DIR must contain both .c and .h files.
> +         If INPUT_DIR and OUTPUT_DIR are the same directory,
> +         psu_init_gpl.c will be overwritten.
> +
> +EOF
> +}
> +
> +set -o errexit -o errtrace
> +set -o nounset
> +
> +if [ $# -ne 2 ]
> +then
> +    usage >&2
> +    exit 1
> +fi
> +
> +IN="${1}/psu_init_gpl.c"
> +OUT="${2}/psu_init_gpl.c"
> +TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX)
> +trap "rm ${TMP}" ERR
> +
> +# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT
> +sed -e '/sleep.h/d' \
> +    -e '/xil_io.h/d' \
> +    ${IN} >${TMP}
> +cp ${TMP} ${OUT}
> +
> +# preprocess to expand defines, then remove cpp lines starting with '#'
> +gcc -I${1} -E ${OUT} -o ${TMP}
> +sed '/^#/d' ${TMP} >${OUT}
> +
> +# Remove trivial code before psu_pll_init_data()
> +sed -ni '/psu_pll_init_data/,$p' ${OUT}
> +
> +# Functions are lowercase in U-Boot, rename them
> +sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT}
> +sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT}
> +sed -i 's/RegValue/regvalue/g' ${OUT}
> +sed -i 's/MaskStatus/maskstatus/g' ${OUT}
> +
> +sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT}
> +
> +FUNCS_TO_REMOVE="psu_protection
> +psu_..._protection
> +psu_init_xppu_aper_ram
> +mask_delay(u32
> +mask_read(u32
> +dpll_prog
> +mask_poll(u32
> +mask_pollonvalue(u32
> +psu_ps_pl_reset_config_data
> +psu_ps_pl_isolation_removal_data
> +psu_apply_master_tz
> +psu_post_config_data
> +psu_post_config_data
> +psu_peripherals_powerdwn_data
> +psu_init_ddr_self_refresh
> +xmpu
> +xppu
> +"
> +for i in $FUNCS_TO_REMOVE; do
> +sed -i "/$i/,/^}$/d" ${OUT}
> +done
> +
> +scripts/Lindent ${OUT}
> +
> +# Prepend 'static' to internal functions
> +sed -i 's/^.*data(void)$/static &/g' ${OUT}
> +sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT}
> +sed -i 's/^void init_peripheral/static &/g' ${OUT}
> +sed -i 's/^int serdes/static &/g' ${OUT}
> +sed -i 's/^int init_serdes/static &/g' ${OUT}
> +sed -i 's/^unsigned long /static &/g' ${OUT}
> +
> +sed -i 's/()$/(void)/g' ${OUT}
> +sed -i 's/0X/0x/g' ${OUT}
> +
> +# Add header
> +cat << EOF >${TMP}
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
> + */
> +
> +#include <asm/arch/psu_init_gpl.h>
> +#include <xil_io.h>
> +
> +EOF
> +
> +cat ${OUT} >>${TMP}
> +cp ${TMP} ${OUT}
> +
> +# Temporarily convert newlines to do some mangling across lines
> +tr "\n" "\r" <${OUT} >${TMP}
> +
> +# Cleanup empty loops. E.g.:
> +# |while (e) {|
> +# |           | ==> |while (e)|
> +# |    }      |     |    ;    |
> +# |           |
> +sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP}
> +
> +# Remove empty line between variable declaration
> +sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP}
> +
> +# Remove empty lines at function beginning/end
> +sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP}
> +sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP}
> +
> +# Remove empty lines after '{' line
> +sed -i -e 's| {\r\r| {\r|g' ${TMP}
> +
> +# Remove braces {} around single statement blocks. E.g.:
> +# | while (e) { |    | while (e) |
> +# |     stg();  | => |     stg();|
> +# | }           |
> +sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP}
> +
> +# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.:
> +# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...)
> +sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP}
> +
> +# Convert back newlines
> +tr "\r" "\n" <${TMP} >${OUT}
> +
> +rm ${TMP}
> 

Applied.
M

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit
  2019-05-24 13:40 ` [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit Luca Ceresoli
@ 2019-05-28  7:45   ` Michal Simek
  2019-06-11 16:09     ` Luca Ceresoli
  0 siblings, 1 reply; 7+ messages in thread
From: Michal Simek @ 2019-05-28  7:45 UTC (permalink / raw)
  To: u-boot

On 24. 05. 19 15:40, Luca Ceresoli wrote:
> Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
> only publicly-available compatible carrier card. The SoM is based on the EV
> version of the Xilinx ZynqMP SoC+FPGA.
> 
> The psu_init_gpl.c file has been generated from the board definition files
> at [0] using Vivado 2018.3 and then minimized by
> tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
> it is not mentioned in device tree and fixed a checkpatch error.
> 
> [0] https://github.com/Avnet/bdf/tree/3686c9ff7d2f0467fb4fcf39f861b8d6ff183b12/ultrazed_7ev_cc/1.1
> 
> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
> 
> ---
> 
> Changes v1 -> v2:
>  - remove serdes code from psu_init_gpl.c since no serdes is enabled in DT
>    (Michal)
>  - split DT in two files: SOM and carrier card (Michal)
>  - improved DT comments, added product URLs
>  - DT: add missing phy-handle under ethernet node (Michal)
> 
> Whole patchset tested on:
>  - current u-boot/master, as is
>  - current u-boot-microblaze/master
>  - current u-boot-microblaze/master with the addtion of
>    commit f89d6133eef2 ("configs: move CONFIG_SPL_TEXT_BASE to Kconfig")
> ---
>  arch/arm/dts/Makefile                         |   1 +
>  arch/arm/dts/avnet-ultrazedev-cc.dts          |  58 ++
>  arch/arm/dts/avnet-ultrazedev-som.dtsi        |  54 ++
>  .../zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c | 663 ++++++++++++++++++
>  configs/avnet_ultrazedev_defconfig            |  64 ++
>  5 files changed, 840 insertions(+)
>  create mode 100644 arch/arm/dts/avnet-ultrazedev-cc.dts
>  create mode 100644 arch/arm/dts/avnet-ultrazedev-som.dtsi
>  create mode 100644 board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
>  create mode 100644 configs/avnet_ultrazedev_defconfig

I am still not happy with this one. Boards have certain revisions which
is not reflected anywhere. Please add it model and also to file name.
I am missing model property - there should be one in SOM. And another
one for carrier card.

I had similar thing recently about how to name board with specific FMC
card.
Name is composed like this
<board_name>-<board_revision>-<fmc_name>-<fmc_revision>.dts

And the same style should be used here.
avnet-ultrazedev-cc-revC-ultrazedev-som-revA.dts

It is longer but it describe that configuration fully.
When new som is added to the same base you can put that stuff together.


> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8167cdb4e856..d82dc6529749 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
>  	zynq-zybo-z7.dtb
>  dtb-$(CONFIG_ARCH_ZYNQMP) += \
>  	avnet-ultra96-rev1.dtb			\
> +	avnet-ultrazedev-cc.dtb			\
>  	zynqmp-mini.dtb				\
>  	zynqmp-mini-emmc0.dtb			\
>  	zynqmp-mini-emmc1.dtb			\
> diff --git a/arch/arm/dts/avnet-ultrazedev-cc.dts b/arch/arm/dts/avnet-ultrazedev-cc.dts
> new file mode 100644
> index 000000000000..d94dd4246f7b
> --- /dev/null
> +++ b/arch/arm/dts/avnet-ultrazedev-cc.dts
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +
> +/*
> + * UltraZed-EV Carrier Card (based on the UltraZed-EV SoM)
> + * http://ultrazed.org/product/ultrazed-ev-carrier-card
> + */
> +
> +/dts-v1/;
> +
> +#include "avnet-ultrazedev-som.dtsi"
> +
> +/ {

please add model and compatibility here.

> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +		xlnx,eeprom = &eeprom;
> +	};
> +	aliases {
> +		ethernet0 = &gem3;
> +		serial0 = &uart0;
> +	};
> +};
> +
> +&uart0 {
> +	device_type = "serial";
> +	port-number = <0>;

This property shouldn't be needed.

> +	status = "okay";
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&i2c_cc {
> +	/* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
> +	eeprom: eeprom at 51 {
> +		compatible = "at,24c02", "i2c-eeprom";

please remove i2c-eeprom - this is just u-boot thing and

at,24c02 should replaced by atmel,24c02. Done in kernel some time ago.


> +		reg = <0x51>;
> +	};
> +
> +	/* IDT Versa Clock 5P49V5935B */
> +	vc5: clock-generator at 6a {
> +		compatible = "idt,5p49v5935";
> +		reg = <0x6a>;
> +		#clock-cells = <1>;
> +	};
> +};
> +
> +/* Ethernet RJ-45 */
> +&gem3 {
> +	status = "okay";
> +};
> +
> +/* microSD card slot */
> +&sdhci1 {
> +	status = "okay";
> +	xlnx,mio_bank = <1>;
> +	clock-frequency = <199998000>;
> +	max-frequency = <50000000>;
> +	no-1-8-v;
> +	disable-wp;
> +};
> diff --git a/arch/arm/dts/avnet-ultrazedev-som.dtsi b/arch/arm/dts/avnet-ultrazedev-som.dtsi
> new file mode 100644
> index 000000000000..4ce0a2d31786
> --- /dev/null
> +++ b/arch/arm/dts/avnet-ultrazedev-som.dtsi
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +
> +/*
> + * UltraZed-EV SoM
> + * http://ultrazed.org/product/ultrazed-ev
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> +
> +/ {

model/compatible string here.

> +	memory {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
> +		      <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	i2cswitch at 70 {
> +		compatible = "nxp,pca9543";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0x70>;
> +
> +		/* I2C connected to Carrier Card via JX3A1/JX3C1 */
> +		i2c_cc: i2c at 0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
> +/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
> +&gem3 {
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&gem3phy>;
> +	gem3phy: phy at 0 {

I know that I have it incorrectly too. But this should be
gem3phy: ethernet-phy at 0 {

> +		reg = <0x0>;

nit - just 0

> +	};
> +};
> +
> +/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
> +&sdhci0 {
> +	status = "okay";
> +	xlnx,mio_bank = <0>;
> +	clock-frequency = <199998000>;
> +};
> diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
> new file mode 100644
> index 000000000000..68dcd2d2af9e
> --- /dev/null
> +++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc/psu_init_gpl.c
> @@ -0,0 +1,663 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
> + */
> +
> +#include <asm/arch/psu_init_gpl.h>
> +#include <xil_io.h>
> +
> +static unsigned long psu_pll_init_data(void)
> +{
> +	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
> +	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
> +	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
> +	mask_poll(0xFF5E0040, 0x00000002U);
> +	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
> +	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
> +	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
> +	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
> +	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
> +	mask_poll(0xFF5E0040, 0x00000001U);
> +	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
> +	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
> +	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
> +	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
> +	mask_poll(0xFD1A0044, 0x00000001U);
> +	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
> +	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
> +	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
> +	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
> +	mask_poll(0xFD1A0044, 0x00000002U);
> +	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
> +	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
> +	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
> +	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
> +	mask_poll(0xFD1A0044, 0x00000004U);
> +	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_clock_init_data(void)
> +{
> +	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
> +	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
> +	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
> +	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
> +	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
> +	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
> +	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
> +	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
> +	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
> +	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
> +	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
> +	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
> +	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
> +	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
> +	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
> +	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
> +	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
> +	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
> +	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
> +	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
> +	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
> +	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
> +	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
> +	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
> +	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
> +	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
> +	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
> +	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
> +	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
> +	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
> +	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
> +	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
> +	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
> +	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
> +	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
> +	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
> +	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
> +	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
> +	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
> +	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_ddr_init_data(void)
> +{
> +	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
> +	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
> +	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
> +	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
> +	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
> +	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
> +	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
> +	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
> +	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
> +	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
> +	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
> +	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
> +	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
> +	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
> +	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
> +	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
> +	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
> +	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
> +	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
> +	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
> +	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
> +	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
> +	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
> +	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
> +	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
> +	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
> +	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
> +	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
> +	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
> +	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
> +	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
> +	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
> +	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
> +	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
> +	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
> +	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
> +	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
> +	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
> +	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
> +	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
> +	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
> +	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
> +	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
> +	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
> +	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
> +	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
> +	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
> +	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
> +	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
> +	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
> +	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
> +	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
> +	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
> +	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
> +	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
> +	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
> +	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
> +	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
> +	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
> +	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
> +	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
> +	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
> +	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
> +	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
> +	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
> +	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
> +	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
> +	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
> +	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
> +	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
> +	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
> +	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
> +	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
> +	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
> +	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
> +	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
> +	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
> +	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
> +	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
> +	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
> +	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
> +	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
> +	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
> +	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
> +	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
> +	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
> +	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
> +	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
> +	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
> +	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
> +	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
> +	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
> +	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
> +	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
> +	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
> +	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
> +	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
> +	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
> +	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
> +	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
> +	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
> +	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
> +	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
> +	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
> +	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
> +	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
> +	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
> +	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
> +	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
> +	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
> +	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
> +	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
> +	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
> +	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
> +	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
> +	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
> +	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
> +	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
> +	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
> +	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
> +	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
> +	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
> +	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
> +	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
> +	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
> +	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
> +	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
> +	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
> +	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
> +	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
> +	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
> +	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
> +	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
> +	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
> +	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
> +	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
> +	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
> +	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
> +	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
> +	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
> +	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
> +	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
> +	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
> +	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
> +	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
> +	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
> +	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
> +	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
> +	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
> +	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
> +	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
> +	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
> +	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
> +	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
> +	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
> +	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
> +	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
> +	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
> +	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
> +	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
> +	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
> +	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
> +	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
> +	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
> +	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
> +	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
> +	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
> +	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
> +	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
> +	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
> +	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_ddr_qos_init_data(void)
> +{
> +	return 1;
> +}
> +
> +static unsigned long psu_mio_init_data(void)
> +{
> +	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
> +	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
> +	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
> +	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
> +	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
> +	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
> +	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
> +	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
> +	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
> +	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
> +	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
> +	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
> +	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
> +	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
> +	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
> +	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
> +	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
> +	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_peripherals_pre_init_data(void)
> +{
> +	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_peripherals_init_data(void)
> +{
> +	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
> +	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
> +	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
> +	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
> +	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
> +	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
> +	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
> +	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
> +	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
> +	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
> +	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
> +	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
> +	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
> +	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
> +	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
> +	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
> +	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
> +	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
> +	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
> +	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
> +	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
> +	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
> +	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
> +	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
> +	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
> +	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
> +	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
> +	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
> +	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
> +	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
> +
> +	mask_delay(1);
> +	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
> +
> +	mask_delay(5);
> +	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
> +	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
> +	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
> +	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
> +	mask_delay(1);
> +	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
> +	mask_delay(5);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_afi_config(void)
> +{
> +	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
> +	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
> +	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
> +
> +	return 1;
> +}
> +
> +static unsigned long psu_ddr_phybringup_data(void)
> +{
> +	unsigned int regval = 0;
> +	unsigned int pll_retry = 10;
> +	unsigned int pll_locked = 0;
> +
> +	while ((pll_retry > 0) && (!pll_locked)) {
> +		Xil_Out32(0xFD080004, 0x00040010);
> +		Xil_Out32(0xFD080004, 0x00040011);
> +
> +		while ((Xil_In32(0xFD080030) & 0x1) != 1)
> +			;
> +		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
> +		    >> 31;
> +		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
> +		    >> 16;
> +		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
> +		    >> 16;
> +		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
> +		    >> 16;
> +		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
> +		    >> 16;
> +		pll_retry--;
> +	}
> +	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
> +	if (!pll_locked)
> +		return (0);

nit: return 0;

> +
> +	Xil_Out32(0xFD080004U, 0x00040063U);
> +
> +	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
> +		;
> +	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
> +
> +	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
> +		;
> +	Xil_Out32(0xFD0701B0U, 0x00000001U);
> +	Xil_Out32(0xFD070320U, 0x00000001U);
> +	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
> +		;
> +	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
> +	Xil_Out32(0xFD080004, 0x0004FE01);
> +	regval = Xil_In32(0xFD080030);
> +	while (regval != 0x80000FFF)
> +		regval = Xil_In32(0xFD080030);
> +	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
> +	if (regval != 0)
> +		return (0);

ditto.

> +
> +	Xil_Out32(0xFD080200U, 0x100091C7U);
> +	int cur_R006_tREFPRD;
> +
> +	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
> +	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
> +
> +	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
> +	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
> +	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
> +	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
> +	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
> +	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
> +
> +	Xil_Out32(0xFD080004, 0x00060001);
> +	regval = Xil_In32(0xFD080030);
> +	while ((regval & 0x80004001) != 0x80004001)
> +		regval = Xil_In32(0xFD080030);
> +
> +	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
> +	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
> +	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
> +	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
> +	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
> +	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
> +
> +	Xil_Out32(0xFD080200U, 0x800091C7U);
> +	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
> +
> +	Xil_Out32(0xFD080004, 0x0000C001);
> +	regval = Xil_In32(0xFD080030);
> +	while ((regval & 0x80000C01) != 0x80000C01)
> +		regval = Xil_In32(0xFD080030);
> +
> +	Xil_Out32(0xFD070180U, 0x01000040U);
> +	Xil_Out32(0xFD070060U, 0x00000000U);
> +	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
> +
> +	return 1;
> +}
> +
> +static void init_peripheral(void)
> +{
> +	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
> +}
> +
> +int psu_init(void)
> +{
> +	int status = 1;
> +
> +	status &= psu_mio_init_data();
> +	status &= psu_peripherals_pre_init_data();
> +	status &= psu_pll_init_data();
> +	status &= psu_clock_init_data();
> +	status &= psu_ddr_init_data();
> +	status &= psu_ddr_phybringup_data();
> +	status &= psu_peripherals_init_data();
> +	init_peripheral();
> +
> +	status &= psu_afi_config();
> +	psu_ddr_qos_init_data();
> +
> +	if (status == 0)
> +		return 1;
> +	return 0;
> +}
> diff --git a/configs/avnet_ultrazedev_defconfig b/configs/avnet_ultrazedev_defconfig
> new file mode 100644
> index 000000000000..6da8283aef9f
> --- /dev/null
> +++ b/configs/avnet_ultrazedev_defconfig
> @@ -0,0 +1,64 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ZYNQMP=y
> +CONFIG_SYS_TEXT_BASE=0x8000000
> +CONFIG_SYS_MALLOC_F_LEN=0x8000
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0xff000000
> +CONFIG_DEBUG_UART_CLOCK=100000000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_BOOTDELAY=0
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_TEXT_BASE=0xfffc0000
> +CONFIG_SPL_OS_BOOT=y
> +CONFIG_SYS_PROMPT="ZynqMP> "
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_FPGA_LOADBP=y
> +CONFIG_CMD_FPGA_LOADP=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc"
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_CLK_ZYNQMP=y
> +CONFIG_FPGA_XILINX=y
> +CONFIG_FPGA_ZYNQMPPL=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_CADENCE=y
> +CONFIG_I2C_MUX=y
> +CONFIG_I2C_MUX_PCA954x=y
> +CONFIG_MISC=y
> +CONFIG_I2C_EEPROM=y
> +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ZYNQ=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SF_DUAL_FLASH=y
> +CONFIG_SPI_FLASH_ISSI=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_ZYNQ_GEM=y
> +CONFIG_DEBUG_UART_ZYNQ=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_ZYNQ_SERIAL=y
> +CONFIG_SPI=y
> +CONFIG_ZYNQMP_GQSPI=y
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
> 

The rest is fine.

Thanks,
Michal

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit
  2019-05-28  7:45   ` Michal Simek
@ 2019-06-11 16:09     ` Luca Ceresoli
  0 siblings, 0 replies; 7+ messages in thread
From: Luca Ceresoli @ 2019-06-11 16:09 UTC (permalink / raw)
  To: u-boot

Hi Michal,

On 28/05/19 09:45, Michal Simek wrote:
[...]
>> +static unsigned long psu_ddr_phybringup_data(void)
>> +{
>> +	unsigned int regval = 0;
>> +	unsigned int pll_retry = 10;
>> +	unsigned int pll_locked = 0;
>> +
>> +	while ((pll_retry > 0) && (!pll_locked)) {
>> +		Xil_Out32(0xFD080004, 0x00040010);
>> +		Xil_Out32(0xFD080004, 0x00040011);
>> +
>> +		while ((Xil_In32(0xFD080030) & 0x1) != 1)
>> +			;
>> +		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
>> +		    >> 31;
>> +		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
>> +		    >> 16;
>> +		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
>> +		    >> 16;
>> +		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
>> +		    >> 16;
>> +		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
>> +		    >> 16;
>> +		pll_retry--;
>> +	}
>> +	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
>> +	if (!pll_locked)
>> +		return (0);
> 
> nit: return 0;

In v3 I'm sending a new patch to let tools/zynqmp_psu_init_minimize.sh
do it automatically.

Ok for the other change requests too, will be in v3.

-- 
Luca

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-06-11 16:09 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-24 13:40 [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Luca Ceresoli
2019-05-24 13:40 ` [U-Boot] [PATCH v2 2/3] arm64: zynqmp: add tool to minimize psu_init_gpl.c files Luca Ceresoli
2019-05-28  6:29   ` Michal Simek
2019-05-24 13:40 ` [U-Boot] [PATCH v2 3/3] arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit Luca Ceresoli
2019-05-28  7:45   ` Michal Simek
2019-06-11 16:09     ` Luca Ceresoli
2019-05-28  6:29 ` [U-Boot] [PATCH v2 1/3] arm64: zynqmp: xil_io.h: declare functions as static Michal Simek

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