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[184.163.105.249]) by smtp.gmail.com with ESMTPSA id q69sm4746371vsd.10.2019.05.27.07.20.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 27 May 2019 07:20:38 -0700 (PDT) Date: Mon, 27 May 2019 10:20:37 -0400 Message-ID: <20190527102037.GB31320@t480s.localdomain> From: Vivien Didelot To: Rasmus Villemoes Cc: Florian Fainelli , Andrew Lunn , Network Development Subject: Re: reset value of MV88E6XXX_G1_IEEE_PRI In-Reply-To: <493a84d0-5319-41ce-1437-77daf8813d39@prevas.dk> References: <4e5592a2-bce3-127b-99e1-7fab00dc0511@prevas.dk> <20190527083215.GB2594@t480s.localdomain> <493a84d0-5319-41ce-1437-77daf8813d39@prevas.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Rasmus, On Mon, 27 May 2019 13:02:04 +0000, Rasmus Villemoes wrote: > > On Mon, 27 May 2019 09:36:13 +0000, Rasmus Villemoes wrote: > >> Looking through the data sheets comparing the mv88e6240 and 6250, I > >> noticed that they have the exact same description of the G1_IEEE_PRI > >> register (global1, offset 0x18). However, the current code used by 6240 does > >> > >> int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) > >> { > >> /* Reset the IEEE Tag priorities to defaults */ > >> return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); > >> } > >> > >> while if my reading of the data sheet is correct, the reset value is > >> really 0xfa50 (fields 7:6 and 5:4 are RWS to 0x1, field 3:2 and 1:0 are > >> RWR) - and this is also the value I read from the 6250 on our old BSP > >> with an out-of-tree driver that doesn't touch that register. This seems > >> to go way back (at least 3b1588593097). Should this be left alone for > >> not risking breaking existing setups (just updating the comment), or can > >> we make the code match the comment? Or am I just reading this all wrong? > > > > If the reset value isn't the same, the bits are certainly differently > > organized inside this register, so the proper way would be to add a > > mv88e6240_g1_ieee_pri_map function, used by both 88E6240 and 88E6250. > > > > Based on the very systematic description [ieee tags 7 and 6 are mapped > to 3, 5 and 4 to 2, 3 and 2 to 1, and 1 and 0 to 0], I strongly believe > that 0xfa50 is also the reset value for the 6085, so this is most likely > wrong for all the current chips - though I don't have a 6085 data sheet. > > I can certainly add a 6250 variant that does the right thing for the > 6250, and I probably will - this is more a question about the current code. Good catch, I double checked 88E6085 and 88E6352 and both describe a reset value of 0xFA50. Fixing mv88e6085_g1_ieee_pri_map should be enough. > > > I'm not a big fan of rewriting the default values, but that is the > > way we chose until we make actually use of these tag priority bits. > > Yes, I was wondering why there's a lot of code which simply serves to > set default values - but I guess it makes sense to force the switch into > a known state in case the bootloader did something odd. That was the idea, yes. Thank you, Vivien