From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B53B2C04AB6 for ; Tue, 28 May 2019 12:27:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 970C1208CB for ; Tue, 28 May 2019 12:27:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727032AbfE1M12 (ORCPT ); Tue, 28 May 2019 08:27:28 -0400 Received: from muru.com ([72.249.23.125]:51564 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726620AbfE1M11 (ORCPT ); Tue, 28 May 2019 08:27:27 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 4B06480F3; Tue, 28 May 2019 12:27:45 +0000 (UTC) Date: Tue, 28 May 2019 05:27:22 -0700 From: Tony Lindgren To: David Laight Cc: "linux-omap@vger.kernel.org" , Dave Gerlach , Faiz Abbas , Greg Kroah-Hartman , Keerthy , Nishanth Menon , Peter Ujfalusi , Roger Quadros , Suman Anna , Tero Kristo , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Rob Herring , "devicetree@vger.kernel.org" Subject: Re: [PATCH 01/12] bus: ti-sysc: Support 16-bit writes too Message-ID: <20190528122722.GO5447@atomide.com> References: <20190527121348.45251-1-tony@atomide.com> <20190527121348.45251-2-tony@atomide.com> <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * David Laight [190528 11:06]: > From: Tony Lindgren > > Sent: 27 May 2019 13:14 > > We need to also support 16-bit writes for i2c in addition to the reads > > when we start configuring the sysconfig register for reset and idle modes. > > > > Signed-off-by: Tony Lindgren > > --- > > drivers/bus/ti-sysc.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c > > --- a/drivers/bus/ti-sysc.c > > +++ b/drivers/bus/ti-sysc.c > > @@ -100,6 +100,13 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, > > > > static void sysc_write(struct sysc *ddata, int offset, u32 value) > > { > > + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { > > + writew_relaxed(value & 0xffff, ddata->module_va + offset); > > + writew_relaxed(value >> 16, ddata->module_va + offset + 4); > > Should that be + 2 ??? Well the stride for I2C revision registers is 4. But while checking that again, I noticed that the other registers do not have HI and LO registers and should just use a single 16-bit read and write. So far it's harmless, but should be fixed. Updated patch below. Regards, Tony 8< ---------------- >From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 May 2019 04:51:53 -0700 Subject: [PATCH] bus: ti-sysc: Support 16-bit writes too We need to also support 16-bit writes for i2c in addition to the reads when we start configuring the sysconfig register for reset and idle modes. Note that only i2c revision register has LO and HI registers, so let's add a check also for 16-bit register read. This change is currently cosmetic and does not affect anything until we enable the module specific quirk handling for i2c reset and enable later on. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -100,6 +100,20 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, static void sysc_write(struct sysc *ddata, int offset, u32 value) { + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { + writew_relaxed(value & 0xffff, ddata->module_va + offset); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 hi = value >> 16; + + writew_relaxed(hi, ddata->module_va + offset + 4); + } + + return; + } + writel_relaxed(value, ddata->module_va + offset); } @@ -109,7 +123,14 @@ static u32 sysc_read(struct sysc *ddata, int offset) u32 val; val = readw_relaxed(ddata->module_va + offset); - val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 tmp = readw_relaxed(ddata->module_va + offset + 4); + + val |= tmp << 16; + } return val; } -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH 01/12] bus: ti-sysc: Support 16-bit writes too Date: Tue, 28 May 2019 05:27:22 -0700 Message-ID: <20190528122722.GO5447@atomide.com> References: <20190527121348.45251-1-tony@atomide.com> <20190527121348.45251-2-tony@atomide.com> <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> Sender: linux-kernel-owner@vger.kernel.org To: David Laight Cc: "linux-omap@vger.kernel.org" , Dave Gerlach , Faiz Abbas , Greg Kroah-Hartman , Keerthy , Nishanth Menon , Peter Ujfalusi , Roger Quadros , Suman Anna , Tero Kristo , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Rob Herring , "devicetree@vger.kernel.org" List-Id: devicetree@vger.kernel.org * David Laight [190528 11:06]: > From: Tony Lindgren > > Sent: 27 May 2019 13:14 > > We need to also support 16-bit writes for i2c in addition to the reads > > when we start configuring the sysconfig register for reset and idle modes. > > > > Signed-off-by: Tony Lindgren > > --- > > drivers/bus/ti-sysc.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c > > --- a/drivers/bus/ti-sysc.c > > +++ b/drivers/bus/ti-sysc.c > > @@ -100,6 +100,13 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, > > > > static void sysc_write(struct sysc *ddata, int offset, u32 value) > > { > > + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { > > + writew_relaxed(value & 0xffff, ddata->module_va + offset); > > + writew_relaxed(value >> 16, ddata->module_va + offset + 4); > > Should that be + 2 ??? Well the stride for I2C revision registers is 4. But while checking that again, I noticed that the other registers do not have HI and LO registers and should just use a single 16-bit read and write. So far it's harmless, but should be fixed. Updated patch below. Regards, Tony 8< ---------------- >>From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 May 2019 04:51:53 -0700 Subject: [PATCH] bus: ti-sysc: Support 16-bit writes too We need to also support 16-bit writes for i2c in addition to the reads when we start configuring the sysconfig register for reset and idle modes. Note that only i2c revision register has LO and HI registers, so let's add a check also for 16-bit register read. This change is currently cosmetic and does not affect anything until we enable the module specific quirk handling for i2c reset and enable later on. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -100,6 +100,20 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, static void sysc_write(struct sysc *ddata, int offset, u32 value) { + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { + writew_relaxed(value & 0xffff, ddata->module_va + offset); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 hi = value >> 16; + + writew_relaxed(hi, ddata->module_va + offset + 4); + } + + return; + } + writel_relaxed(value, ddata->module_va + offset); } @@ -109,7 +123,14 @@ static u32 sysc_read(struct sysc *ddata, int offset) u32 val; val = readw_relaxed(ddata->module_va + offset); - val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 tmp = readw_relaxed(ddata->module_va + offset + 4); + + val |= tmp << 16; + } return val; } -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3991EC072B1 for ; Tue, 28 May 2019 12:27:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12B87208C3 for ; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hVbCU-0001Vb-WC; Tue, 28 May 2019 12:27:31 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hVbCS-0001V4-5C for linux-arm-kernel@lists.infradead.org; Tue, 28 May 2019 12:27:29 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 4B06480F3; Tue, 28 May 2019 12:27:45 +0000 (UTC) Date: Tue, 28 May 2019 05:27:22 -0700 From: Tony Lindgren To: David Laight Subject: Re: [PATCH 01/12] bus: ti-sysc: Support 16-bit writes too Message-ID: <20190528122722.GO5447@atomide.com> References: <20190527121348.45251-1-tony@atomide.com> <20190527121348.45251-2-tony@atomide.com> <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5e9a31dfdfd843469c51106fce9ea353@AcuMS.aculab.com> User-Agent: Mutt/1.11.4 (2019-03-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190528_052728_242028_2337F352 X-CRM114-Status: GOOD ( 19.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Tero Kristo , Suman Anna , Dave Gerlach , Keerthy , "linux-kernel@vger.kernel.org" , Peter Ujfalusi , "devicetree@vger.kernel.org" , Faiz Abbas , Greg Kroah-Hartman , "linux-omap@vger.kernel.org" , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Roger Quadros Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org * David Laight [190528 11:06]: > From: Tony Lindgren > > Sent: 27 May 2019 13:14 > > We need to also support 16-bit writes for i2c in addition to the reads > > when we start configuring the sysconfig register for reset and idle modes. > > > > Signed-off-by: Tony Lindgren > > --- > > drivers/bus/ti-sysc.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c > > --- a/drivers/bus/ti-sysc.c > > +++ b/drivers/bus/ti-sysc.c > > @@ -100,6 +100,13 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, > > > > static void sysc_write(struct sysc *ddata, int offset, u32 value) > > { > > + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { > > + writew_relaxed(value & 0xffff, ddata->module_va + offset); > > + writew_relaxed(value >> 16, ddata->module_va + offset + 4); > > Should that be + 2 ??? Well the stride for I2C revision registers is 4. But while checking that again, I noticed that the other registers do not have HI and LO registers and should just use a single 16-bit read and write. So far it's harmless, but should be fixed. Updated patch below. Regards, Tony 8< ---------------- >From tony Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 May 2019 04:51:53 -0700 Subject: [PATCH] bus: ti-sysc: Support 16-bit writes too We need to also support 16-bit writes for i2c in addition to the reads when we start configuring the sysconfig register for reset and idle modes. Note that only i2c revision register has LO and HI registers, so let's add a check also for 16-bit register read. This change is currently cosmetic and does not affect anything until we enable the module specific quirk handling for i2c reset and enable later on. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -100,6 +100,20 @@ static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, static void sysc_write(struct sysc *ddata, int offset, u32 value) { + if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { + writew_relaxed(value & 0xffff, ddata->module_va + offset); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 hi = value >> 16; + + writew_relaxed(hi, ddata->module_va + offset + 4); + } + + return; + } + writel_relaxed(value, ddata->module_va + offset); } @@ -109,7 +123,14 @@ static u32 sysc_read(struct sysc *ddata, int offset) u32 val; val = readw_relaxed(ddata->module_va + offset); - val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); + + /* Only i2c revision has LO and HI register with stride of 4 */ + if (ddata->offsets[SYSC_REVISION] >= 0 && + offset == ddata->offsets[SYSC_REVISION]) { + u16 tmp = readw_relaxed(ddata->module_va + offset + 4); + + val |= tmp << 16; + } return val; } -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel