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* [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02  8:04 ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv

Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
architectures.  Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.

This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.

Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.

This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:

https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1


- Paul


Paul Walmsley (5):
  arch: riscv: add support for building DTB files from DT source data
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive
    FU540
  dt-bindings: riscv: convert cpu binding to json-schema
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  riscv: dts: add initial board data for the SiFive HiFive Unleashed

 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++
 .../devicetree/bindings/riscv/sifive.yaml     |  25 ++
 MAINTAINERS                                   |   9 +
 arch/riscv/boot/dts/Makefile                  |   2 +
 arch/riscv/boot/dts/sifive/Makefile           |   2 +
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 215 ++++++++++++++++++
 .../boot/dts/sifive/hifive-unleashed-a00.dts  |  67 ++++++
 7 files changed, 488 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
 create mode 100644 arch/riscv/boot/dts/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

-- 
2.20.1


^ permalink raw reply	[flat|nested] 55+ messages in thread

* [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02  8:04 ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv

Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
architectures.  Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.

This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.

Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.

This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:

https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1


- Paul


Paul Walmsley (5):
  arch: riscv: add support for building DTB files from DT source data
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive
    FU540
  dt-bindings: riscv: convert cpu binding to json-schema
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  riscv: dts: add initial board data for the SiFive HiFive Unleashed

 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++
 .../devicetree/bindings/riscv/sifive.yaml     |  25 ++
 MAINTAINERS                                   |   9 +
 arch/riscv/boot/dts/Makefile                  |   2 +
 arch/riscv/boot/dts/sifive/Makefile           |   2 +
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 215 ++++++++++++++++++
 .../boot/dts/sifive/hifive-unleashed-a00.dts  |  67 ++++++
 7 files changed, 488 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
 create mode 100644 arch/riscv/boot/dts/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-02  8:04   ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv; +Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou

Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.

This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors would add support here in a similar form.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
---
 arch/riscv/boot/dts/Makefile | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 arch/riscv/boot/dts/Makefile

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 000000000000..dcc3ada78455
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-y += sifive
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-02  8:04   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv; +Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou

Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.

This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors would add support here in a similar form.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
---
 arch/riscv/boot/dts/Makefile | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 arch/riscv/boot/dts/Makefile

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 000000000000..dcc3ada78455
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-y += sifive
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-02  8:04   ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Paul Walmsley, Rob Herring, Mark Rutland, Palmer Dabbelt,
	Albert Ou, devicetree

Add YAML DT binding documentation for the SiFive FU540 SoC.  This
SoC is documented at:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.

This second version incorporates review feedback from Rob Herring
<robh@kernel.org>.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
 MAINTAINERS                                   |  9 +++++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml

diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
new file mode 100644
index 000000000000..ce7ca191789e
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive SoC-based boards
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+
+description:
+  SiFive SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    items:
+      - enum:
+          - sifive,freedom-unleashed-a00
+      - const: sifive,fu540-c000
+      - const: sifive,fu540
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 5cfbea4ce575..8a64051cf5fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14322,6 +14322,15 @@ S:	Supported
 K:	sifive
 N:	sifive
 
+SIFIVE FU540 SYSTEM-ON-CHIP
+M:	Paul Walmsley <paul.walmsley@sifive.com>
+M:	Palmer Dabbelt <palmer@sifive.com>
+L:	linux-riscv@lists.infradead.org
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
+S:	Supported
+K:	fu540
+N:	fu540
+
 SILEAD TOUCHSCREEN DRIVER
 M:	Hans de Goede <hdegoede@redhat.com>
 L:	linux-input@vger.kernel.org
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
@ 2019-06-02  8:04   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring

Add YAML DT binding documentation for the SiFive FU540 SoC.  This
SoC is documented at:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.

This second version incorporates review feedback from Rob Herring
<robh@kernel.org>.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
 MAINTAINERS                                   |  9 +++++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml

diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
new file mode 100644
index 000000000000..ce7ca191789e
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive SoC-based boards
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+
+description:
+  SiFive SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    items:
+      - enum:
+          - sifive,freedom-unleashed-a00
+      - const: sifive,fu540-c000
+      - const: sifive,fu540
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 5cfbea4ce575..8a64051cf5fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14322,6 +14322,15 @@ S:	Supported
 K:	sifive
 N:	sifive
 
+SIFIVE FU540 SYSTEM-ON-CHIP
+M:	Paul Walmsley <paul.walmsley@sifive.com>
+M:	Palmer Dabbelt <palmer@sifive.com>
+L:	linux-riscv@lists.infradead.org
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
+S:	Supported
+K:	fu540
+N:	fu540
+
 SILEAD TOUCHSCREEN DRIVER
 M:	Hans de Goede <hdegoede@redhat.com>
 L:	linux-input@vger.kernel.org
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema
  2019-06-02  8:04 ` Paul Walmsley
  (?)
@ 2019-06-02  8:04   ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Paul Walmsley, Rob Herring, Mark Rutland, Lorenzo Pieralisi, devicetree

At Rob's request, we're starting to migrate our DT binding
documentation to json-schema YAML format.  Start by converting our cpu
binding documentation.  While doing so, document more properties and
nodes.  This includes adding binding documentation support for the E51
and U54 CPU cores ("harts") that are present on this SoC.  These cores
are described in:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

This cpus.yaml file is intended to be a starting point and to
evolve over time.  It passes dt-doc-validate as of the yaml-bindings
commit 4c79d42e9216.

This patch was originally based on the ARM json-schema binding
documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert
cpu binding to json-schema").

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
---
 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++++++
 1 file changed, 168 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
new file mode 100644
index 000000000000..6e8d55d9d4e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V bindings for 'cpus' DT nodes
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+
+allOf:
+  - $ref: /schemas/cpus.yaml#
+
+properties:
+  $nodename:
+    const: cpus
+    description: Container of cpu nodes
+
+  '#address-cells':
+    const: 1
+    description: |
+      A single unsigned 32-bit integer uniquely identifies each RISC-V
+      hart in a system.  (See the "reg" node under the "cpu" node,
+      below).
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  '^cpu@[0-9a-f]+$':
+    properties:
+      compatible:
+        type: array
+        items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+        description:
+          Identifies that the hart uses the RISC-V instruction set
+          and identifies the type of the hart.
+
+      mmu-type:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - riscv,sv32
+              - riscv,sv39
+              - riscv,sv48
+        description:
+          Identifies the MMU address translation mode used on this
+          hart.  These values originate from the RISC-V Privileged
+          Specification document, available from
+          https://riscv.org/specifications/
+
+      riscv,isa:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - rv64imac
+              - rv64imafdc
+        description:
+          Identifies the specific RISC-V instruction set architecture
+          supported by the hart.  These are documented in the RISC-V
+          User-Level ISA document, available from
+          https://riscv.org/specifications/
+
+      timebase-frequency:
+        type: integer
+        minimum: 1
+        description:
+          Specifies the clock frequency of the system timer in Hz.
+          This value is common to all harts on a single system image.
+
+      interrupt-controller:
+        type: object
+        description: Describes the CPU's local interrupt controller
+
+        properties:
+          '#interrupt-cells':
+            const: 1
+
+          compatible:
+            const: riscv,cpu-intc
+
+          interrupt-controller: true
+
+        required:
+          - '#interrupt-cells'
+          - compatible
+          - interrupt-controller
+
+    required:
+      - riscv,isa
+      - timebase-frequency
+      - interrupt-controller
+
+examples:
+  - |
+    // Example 1: SiFive Freedom U540G Development Kit
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <1000000>;
+        cpu@0 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <128>;
+                i-cache-size = <16384>;
+                reg = <0>;
+                riscv,isa = "rv64imac";
+                cpu_intc0: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+        cpu@1 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                d-cache-block-size = <64>;
+                d-cache-sets = <64>;
+                d-cache-size = <32768>;
+                d-tlb-sets = <1>;
+                d-tlb-size = <32>;
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <64>;
+                i-cache-size = <32768>;
+                i-tlb-sets = <1>;
+                i-tlb-size = <32>;
+                mmu-type = "riscv,sv39";
+                reg = <1>;
+                riscv,isa = "rv64imafdc";
+                tlb-split;
+                cpu_intc1: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+    };
+
+  - |
+    // Example 2: Spike ISA Simulator with 1 Hart
+    cpus {
+            cpu@0 {
+                    device_type = "cpu";
+                    reg = <0>;
+                    compatible = "riscv";
+                    riscv,isa = "rv64imafdc";
+                    mmu-type = "riscv,sv48";
+                    interrupt-controller {
+                            #interrupt-cells = <1>;
+                            interrupt-controller;
+                            compatible = "riscv,cpu-intc";
+                    };
+            };
+    };
+...
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema
@ 2019-06-02  8:04   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Mark Rutland, Lorenzo Pieralisi, Paul Walmsley, Rob Herring, devicetree

At Rob's request, we're starting to migrate our DT binding
documentation to json-schema YAML format.  Start by converting our cpu
binding documentation.  While doing so, document more properties and
nodes.  This includes adding binding documentation support for the E51
and U54 CPU cores ("harts") that are present on this SoC.  These cores
are described in:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

This cpus.yaml file is intended to be a starting point and to
evolve over time.  It passes dt-doc-validate as of the yaml-bindings
commit 4c79d42e9216.

This patch was originally based on the ARM json-schema binding
documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert
cpu binding to json-schema").

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
---
 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++++++
 1 file changed, 168 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
new file mode 100644
index 000000000000..6e8d55d9d4e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V bindings for 'cpus' DT nodes
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+
+allOf:
+  - $ref: /schemas/cpus.yaml#
+
+properties:
+  $nodename:
+    const: cpus
+    description: Container of cpu nodes
+
+  '#address-cells':
+    const: 1
+    description: |
+      A single unsigned 32-bit integer uniquely identifies each RISC-V
+      hart in a system.  (See the "reg" node under the "cpu" node,
+      below).
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  '^cpu@[0-9a-f]+$':
+    properties:
+      compatible:
+        type: array
+        items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+        description:
+          Identifies that the hart uses the RISC-V instruction set
+          and identifies the type of the hart.
+
+      mmu-type:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - riscv,sv32
+              - riscv,sv39
+              - riscv,sv48
+        description:
+          Identifies the MMU address translation mode used on this
+          hart.  These values originate from the RISC-V Privileged
+          Specification document, available from
+          https://riscv.org/specifications/
+
+      riscv,isa:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - rv64imac
+              - rv64imafdc
+        description:
+          Identifies the specific RISC-V instruction set architecture
+          supported by the hart.  These are documented in the RISC-V
+          User-Level ISA document, available from
+          https://riscv.org/specifications/
+
+      timebase-frequency:
+        type: integer
+        minimum: 1
+        description:
+          Specifies the clock frequency of the system timer in Hz.
+          This value is common to all harts on a single system image.
+
+      interrupt-controller:
+        type: object
+        description: Describes the CPU's local interrupt controller
+
+        properties:
+          '#interrupt-cells':
+            const: 1
+
+          compatible:
+            const: riscv,cpu-intc
+
+          interrupt-controller: true
+
+        required:
+          - '#interrupt-cells'
+          - compatible
+          - interrupt-controller
+
+    required:
+      - riscv,isa
+      - timebase-frequency
+      - interrupt-controller
+
+examples:
+  - |
+    // Example 1: SiFive Freedom U540G Development Kit
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <1000000>;
+        cpu@0 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <128>;
+                i-cache-size = <16384>;
+                reg = <0>;
+                riscv,isa = "rv64imac";
+                cpu_intc0: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+        cpu@1 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                d-cache-block-size = <64>;
+                d-cache-sets = <64>;
+                d-cache-size = <32768>;
+                d-tlb-sets = <1>;
+                d-tlb-size = <32>;
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <64>;
+                i-cache-size = <32768>;
+                i-tlb-sets = <1>;
+                i-tlb-size = <32>;
+                mmu-type = "riscv,sv39";
+                reg = <1>;
+                riscv,isa = "rv64imafdc";
+                tlb-split;
+                cpu_intc1: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+    };
+
+  - |
+    // Example 2: Spike ISA Simulator with 1 Hart
+    cpus {
+            cpu@0 {
+                    device_type = "cpu";
+                    reg = <0>;
+                    compatible = "riscv";
+                    riscv,isa = "rv64imafdc";
+                    mmu-type = "riscv,sv48";
+                    interrupt-controller {
+                            #interrupt-cells = <1>;
+                            interrupt-controller;
+                            compatible = "riscv,cpu-intc";
+                    };
+            };
+    };
+...
-- 
2.20.1

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema
@ 2019-06-02  8:04   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Mark Rutland, Lorenzo Pieralisi, Paul Walmsley, Rob Herring, devicetree

At Rob's request, we're starting to migrate our DT binding
documentation to json-schema YAML format.  Start by converting our cpu
binding documentation.  While doing so, document more properties and
nodes.  This includes adding binding documentation support for the E51
and U54 CPU cores ("harts") that are present on this SoC.  These cores
are described in:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

This cpus.yaml file is intended to be a starting point and to
evolve over time.  It passes dt-doc-validate as of the yaml-bindings
commit 4c79d42e9216.

This patch was originally based on the ARM json-schema binding
documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert
cpu binding to json-schema").

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
---
 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++++++
 1 file changed, 168 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
new file mode 100644
index 000000000000..6e8d55d9d4e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V bindings for 'cpus' DT nodes
+
+maintainers:
+  - Paul Walmsley <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@sifive.com>
+
+allOf:
+  - $ref: /schemas/cpus.yaml#
+
+properties:
+  $nodename:
+    const: cpus
+    description: Container of cpu nodes
+
+  '#address-cells':
+    const: 1
+    description: |
+      A single unsigned 32-bit integer uniquely identifies each RISC-V
+      hart in a system.  (See the "reg" node under the "cpu" node,
+      below).
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  '^cpu@[0-9a-f]+$':
+    properties:
+      compatible:
+        type: array
+        items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+        description:
+          Identifies that the hart uses the RISC-V instruction set
+          and identifies the type of the hart.
+
+      mmu-type:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - riscv,sv32
+              - riscv,sv39
+              - riscv,sv48
+        description:
+          Identifies the MMU address translation mode used on this
+          hart.  These values originate from the RISC-V Privileged
+          Specification document, available from
+          https://riscv.org/specifications/
+
+      riscv,isa:
+        allOf:
+          - $ref: "/schemas/types.yaml#/definitions/string"
+          - enum:
+              - rv64imac
+              - rv64imafdc
+        description:
+          Identifies the specific RISC-V instruction set architecture
+          supported by the hart.  These are documented in the RISC-V
+          User-Level ISA document, available from
+          https://riscv.org/specifications/
+
+      timebase-frequency:
+        type: integer
+        minimum: 1
+        description:
+          Specifies the clock frequency of the system timer in Hz.
+          This value is common to all harts on a single system image.
+
+      interrupt-controller:
+        type: object
+        description: Describes the CPU's local interrupt controller
+
+        properties:
+          '#interrupt-cells':
+            const: 1
+
+          compatible:
+            const: riscv,cpu-intc
+
+          interrupt-controller: true
+
+        required:
+          - '#interrupt-cells'
+          - compatible
+          - interrupt-controller
+
+    required:
+      - riscv,isa
+      - timebase-frequency
+      - interrupt-controller
+
+examples:
+  - |
+    // Example 1: SiFive Freedom U540G Development Kit
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <1000000>;
+        cpu@0 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <128>;
+                i-cache-size = <16384>;
+                reg = <0>;
+                riscv,isa = "rv64imac";
+                cpu_intc0: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+        cpu@1 {
+                clock-frequency = <0>;
+                compatible = "sifive,rocket0", "riscv";
+                d-cache-block-size = <64>;
+                d-cache-sets = <64>;
+                d-cache-size = <32768>;
+                d-tlb-sets = <1>;
+                d-tlb-size = <32>;
+                device_type = "cpu";
+                i-cache-block-size = <64>;
+                i-cache-sets = <64>;
+                i-cache-size = <32768>;
+                i-tlb-sets = <1>;
+                i-tlb-size = <32>;
+                mmu-type = "riscv,sv39";
+                reg = <1>;
+                riscv,isa = "rv64imafdc";
+                tlb-split;
+                cpu_intc1: interrupt-controller {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,cpu-intc";
+                        interrupt-controller;
+                };
+        };
+    };
+
+  - |
+    // Example 2: Spike ISA Simulator with 1 Hart
+    cpus {
+            cpu@0 {
+                    device_type = "cpu";
+                    reg = <0>;
+                    compatible = "riscv";
+                    riscv,isa = "rv64imafdc";
+                    mmu-type = "riscv,sv48";
+                    interrupt-controller {
+                            #interrupt-cells = <1>;
+                            interrupt-controller;
+                            compatible = "riscv,cpu-intc";
+                    };
+            };
+    };
+...
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-02  8:04   ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Paul Walmsley, Rob Herring, Mark Rutland, Palmer Dabbelt,
	Albert Ou, ShihPo Hung, devicetree

Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.

This file is expected to grow as more device drivers are added to the
kernel.

This patch includes a fix to the QSPI memory map due to a
documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
entries for the I2C controller, and merges all DT changes that
formerly were made dynamically by the riscv-pk BBL proxy kernel.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: ShihPo Hung <shihpo.hung@sifive.com>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 +++++++++++++++++++++
 1 file changed, 215 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
new file mode 100644
index 000000000000..3c06ee4b2b29
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu540-prci.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,fu540-c000", "sifive,fu540";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+		cpu0: cpu@0 {
+			compatible = "sifive,e51", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu1: cpu@1 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu2: cpu@2 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu3: cpu@3 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu4: cpu@4 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu4_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+		ranges;
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			riscv,ndev = <53>;
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc 0xffffffff
+				&cpu1_intc 0xffffffff &cpu1_intc 9
+				&cpu2_intc 0xffffffff &cpu2_intc 9
+				&cpu3_intc 0xffffffff &cpu3_intc 9
+				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+		};
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu540-c000-prci";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			clocks = <&hfclk>, <&rtcclk>;
+			#clock-cells = <1>;
+		};
+		uart0: serial@10010000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <4>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+		};
+		uart1: serial@10011000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10011000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <5>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+		};
+		i2c0: i2c@10030000 {
+			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+			reg = <0x0 0x10030000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <50>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi0: spi@10040000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10040000 0x0 0x1000
+			       0x0 0x20000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <51>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi1: spi@10041000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10041000 0x0 0x1000
+			       0x0 0x30000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <52>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi2: spi@10050000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10050000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <6>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC
@ 2019-06-02  8:04   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:04 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring, ShihPo Hung

Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.

This file is expected to grow as more device drivers are added to the
kernel.

This patch includes a fix to the QSPI memory map due to a
documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
entries for the I2C controller, and merges all DT changes that
formerly were made dynamically by the riscv-pk BBL proxy kernel.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: ShihPo Hung <shihpo.hung@sifive.com>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 +++++++++++++++++++++
 1 file changed, 215 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
new file mode 100644
index 000000000000..3c06ee4b2b29
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu540-prci.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,fu540-c000", "sifive,fu540";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+		cpu0: cpu@0 {
+			compatible = "sifive,e51", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu1: cpu@1 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu2: cpu@2 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu3: cpu@3 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu4: cpu@4 {
+			clock-frequency = <0>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu4_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+		ranges;
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			riscv,ndev = <53>;
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc 0xffffffff
+				&cpu1_intc 0xffffffff &cpu1_intc 9
+				&cpu2_intc 0xffffffff &cpu2_intc 9
+				&cpu3_intc 0xffffffff &cpu3_intc 9
+				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+		};
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu540-c000-prci";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			clocks = <&hfclk>, <&rtcclk>;
+			#clock-cells = <1>;
+		};
+		uart0: serial@10010000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <4>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+		};
+		uart1: serial@10011000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10011000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <5>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+		};
+		i2c0: i2c@10030000 {
+			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+			reg = <0x0 0x10030000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <50>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi0: spi@10040000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10040000 0x0 0x1000
+			       0x0 0x20000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <51>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi1: spi@10041000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10041000 0x0 0x1000
+			       0x0 0x30000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <52>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+		qspi2: spi@10050000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10050000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <6>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
-- 
2.20.1


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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-02  8:05   ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:05 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Paul Walmsley, Rob Herring, Mark Rutland, Palmer Dabbelt,
	Albert Ou, devicetree

Add initial board data for the SiFive HiFive Unleashed A00.

Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.

This third version incorporates changes based on more comments from
Rob Herring <robh+dt@kernel.org>.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sifive/Makefile           |  2 +
 .../boot/dts/sifive/hifive-unleashed-a00.dts  | 67 +++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
new file mode 100644
index 000000000000..baaeef9efdcb
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-y += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
new file mode 100644
index 000000000000..1de4ea1577d5
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include "fu540-c000.dtsi"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unleashed A00";
+	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+	chosen {
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <33333333>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+};
+
+&qspi0 {
+	flash@0 {
+		compatible = "issi,is25wp256", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&qspi2 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 55+ messages in thread

* [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-02  8:05   ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-02  8:05 UTC (permalink / raw)
  To: linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring

Add initial board data for the SiFive HiFive Unleashed A00.

Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.

This third version incorporates changes based on more comments from
Rob Herring <robh+dt@kernel.org>.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/riscv/boot/dts/sifive/Makefile           |  2 +
 .../boot/dts/sifive/hifive-unleashed-a00.dts  | 67 +++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
new file mode 100644
index 000000000000..baaeef9efdcb
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-y += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
new file mode 100644
index 000000000000..1de4ea1577d5
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include "fu540-c000.dtsi"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unleashed A00";
+	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+	chosen {
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <33333333>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+};
+
+&qspi0 {
+	flash@0 {
+		compatible = "issi,is25wp256", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&qspi2 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
-- 
2.20.1


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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-04 14:31   ` Loys Ollivier
  -1 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:31 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add support for building flattened DT files from DT source files under
> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> architectures.  Start our board support by adding initial support for
> the SiFive FU540 SoC and the first development board that uses it, the
> SiFive HiFive Unleashed A00.
>
> This third version of the patch set adds I2C data for the chip,
> incorporates all remaining changes that riscv-pk was making
> automatically, and addresses a comment from Rob Herring
> <robh@kernel.org>.
>
> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> BBL and open-source FSBL, with modifications to pass in the DTB
> file generated by these patches.
>
> This patch series can be found, along with the PRCI patch set
> and the DT macro prerequisite patch, at:
>
> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>
>
> - Paul
>

Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed.
Tested-by: Loys Ollivier <lollivier@baylibre.com>

>
> Paul Walmsley (5):
>   arch: riscv: add support for building DTB files from DT source data
>   dt-bindings: riscv: sifive: add YAML documentation for the SiFive
>     FU540
>   dt-bindings: riscv: convert cpu binding to json-schema
>   riscv: dts: add initial support for the SiFive FU540-C000 SoC
>   riscv: dts: add initial board data for the SiFive HiFive Unleashed
>
>  .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++
>  .../devicetree/bindings/riscv/sifive.yaml     |  25 ++
>  MAINTAINERS                                   |   9 +
>  arch/riscv/boot/dts/Makefile                  |   2 +
>  arch/riscv/boot/dts/sifive/Makefile           |   2 +
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 215 ++++++++++++++++++
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  |  67 ++++++
>  7 files changed, 488 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
>  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
>  create mode 100644 arch/riscv/boot/dts/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
>  create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

Note: the -fu540 was dropped from the previous version which results in
a different dtb file.

Loys

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-04 14:31   ` Loys Ollivier
  0 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:31 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add support for building flattened DT files from DT source files under
> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> architectures.  Start our board support by adding initial support for
> the SiFive FU540 SoC and the first development board that uses it, the
> SiFive HiFive Unleashed A00.
>
> This third version of the patch set adds I2C data for the chip,
> incorporates all remaining changes that riscv-pk was making
> automatically, and addresses a comment from Rob Herring
> <robh@kernel.org>.
>
> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> BBL and open-source FSBL, with modifications to pass in the DTB
> file generated by these patches.
>
> This patch series can be found, along with the PRCI patch set
> and the DT macro prerequisite patch, at:
>
> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>
>
> - Paul
>

Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed.
Tested-by: Loys Ollivier <lollivier@baylibre.com>

>
> Paul Walmsley (5):
>   arch: riscv: add support for building DTB files from DT source data
>   dt-bindings: riscv: sifive: add YAML documentation for the SiFive
>     FU540
>   dt-bindings: riscv: convert cpu binding to json-schema
>   riscv: dts: add initial support for the SiFive FU540-C000 SoC
>   riscv: dts: add initial board data for the SiFive HiFive Unleashed
>
>  .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++
>  .../devicetree/bindings/riscv/sifive.yaml     |  25 ++
>  MAINTAINERS                                   |   9 +
>  arch/riscv/boot/dts/Makefile                  |   2 +
>  arch/riscv/boot/dts/sifive/Makefile           |   2 +
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 215 ++++++++++++++++++
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  |  67 ++++++
>  7 files changed, 488 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
>  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
>  create mode 100644 arch/riscv/boot/dts/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
>  create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

Note: the -fu540 was dropped from the previous version which results in
a different dtb file.

Loys

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-02  8:04   ` Paul Walmsley
@ 2019-06-04 14:37     ` Loys Ollivier
  -1 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:37 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Similar to ARM64, add support for building DTB files from DT source
> data for RISC-V boards.
>
> This patch starts with the infrastructure needed for SiFive boards.
> Boards from other vendors would add support here in a similar form.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> ---
>  arch/riscv/boot/dts/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/Makefile
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> new file mode 100644
> index 000000000000..dcc3ada78455
> --- /dev/null
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +subdir-y += sifive

Always build it ?
Any particular reason to drop ARCH_SIFIVE ?

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-04 14:37     ` Loys Ollivier
  0 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:37 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Similar to ARM64, add support for building DTB files from DT source
> data for RISC-V boards.
>
> This patch starts with the infrastructure needed for SiFive boards.
> Boards from other vendors would add support here in a similar form.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> ---
>  arch/riscv/boot/dts/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/Makefile
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> new file mode 100644
> index 000000000000..dcc3ada78455
> --- /dev/null
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +subdir-y += sifive

Always build it ?
Any particular reason to drop ARCH_SIFIVE ?

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC
  2019-06-02  8:04   ` Paul Walmsley
@ 2019-06-04 14:38     ` Loys Ollivier
  -1 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:38 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring, ShihPo Hung

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> This patch includes a fix to the QSPI memory map due to a
> documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
> entries for the I2C controller, and merges all DT changes that
> formerly were made dynamically by the riscv-pk BBL proxy kernel.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: ShihPo Hung <shihpo.hung@sifive.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC
@ 2019-06-04 14:38     ` Loys Ollivier
  0 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:38 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring, ShihPo Hung

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> This patch includes a fix to the QSPI memory map due to a
> documentation bug, found by ShihPo Hung <shihpo.hung@sifive.com>, adds
> entries for the I2C controller, and merges all DT changes that
> formerly were made dynamically by the riscv-pk BBL proxy kernel.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: ShihPo Hung <shihpo.hung@sifive.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

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^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
  2019-06-02  8:05   ` Paul Walmsley
@ 2019-06-04 14:41     ` Loys Ollivier
  -1 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:41 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring

On Sun 02 Jun 2019 at 01:05, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-04 14:41     ` Loys Ollivier
  0 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-04 14:41 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, Rob Herring

On Sun 02 Jun 2019 at 01:05, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Loys Ollivier <lollivier@baylibre.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-02  8:04 ` Paul Walmsley
@ 2019-06-05 17:36   ` Kevin Hilman
  -1 siblings, 0 replies; 55+ messages in thread
From: Kevin Hilman @ 2019-06-05 17:36 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv

Hi Paul,

Paul Walmsley <paul.walmsley@sifive.com> writes:

> Add support for building flattened DT files from DT source files under
> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> architectures.  Start our board support by adding initial support for
> the SiFive FU540 SoC and the first development board that uses it, the
> SiFive HiFive Unleashed A00.
>
> This third version of the patch set adds I2C data for the chip,
> incorporates all remaining changes that riscv-pk was making
> automatically, and addresses a comment from Rob Herring
> <robh@kernel.org>.
>
> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> BBL and open-source FSBL, with modifications to pass in the DTB
> file generated by these patches.

Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
OpenSBI + mainline u-boot (master branch as of today).

Tested-by: Kevin Hilman <khilman@baylibre.com>

> This patch series can be found, along with the PRCI patch set
> and the DT macro prerequisite patch, at:
>
> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1

nit: I only see this series in that branch, not any of the prerequisite
patches you mentioned, which made me assume I could this series alone on
top of v5.2-rc3, which worked just fine.

Kevin

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-05 17:36   ` Kevin Hilman
  0 siblings, 0 replies; 55+ messages in thread
From: Kevin Hilman @ 2019-06-05 17:36 UTC (permalink / raw)
  To: Paul Walmsley, linux-kernel, linux-riscv

Hi Paul,

Paul Walmsley <paul.walmsley@sifive.com> writes:

> Add support for building flattened DT files from DT source files under
> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> architectures.  Start our board support by adding initial support for
> the SiFive FU540 SoC and the first development board that uses it, the
> SiFive HiFive Unleashed A00.
>
> This third version of the patch set adds I2C data for the chip,
> incorporates all remaining changes that riscv-pk was making
> automatically, and addresses a comment from Rob Herring
> <robh@kernel.org>.
>
> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> BBL and open-source FSBL, with modifications to pass in the DTB
> file generated by these patches.

Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
OpenSBI + mainline u-boot (master branch as of today).

Tested-by: Kevin Hilman <khilman@baylibre.com>

> This patch series can be found, along with the PRCI patch set
> and the DT macro prerequisite patch, at:
>
> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1

nit: I only see this series in that branch, not any of the prerequisite
patches you mentioned, which made me assume I could this series alone on
top of v5.2-rc3, which worked just fine.

Kevin

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-05 17:36   ` Kevin Hilman
@ 2019-06-06 23:15     ` Atish Patra
  -1 siblings, 0 replies; 55+ messages in thread
From: Atish Patra @ 2019-06-06 23:15 UTC (permalink / raw)
  To: Kevin Hilman, Paul Walmsley, linux-kernel, linux-riscv

On 6/5/19 10:37 AM, Kevin Hilman wrote:
> Hi Paul,
> 
> Paul Walmsley <paul.walmsley@sifive.com> writes:
> 
>> Add support for building flattened DT files from DT source files under
>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>> architectures.  Start our board support by adding initial support for
>> the SiFive FU540 SoC and the first development board that uses it, the
>> SiFive HiFive Unleashed A00.
>>
>> This third version of the patch set adds I2C data for the chip,
>> incorporates all remaining changes that riscv-pk was making
>> automatically, and addresses a comment from Rob Herring
>> <robh@kernel.org>.
>>
>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>> BBL and open-source FSBL, with modifications to pass in the DTB
>> file generated by these patches.
> 
> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> OpenSBI + mainline u-boot (master branch as of today).
> 
> Tested-by: Kevin Hilman <khilman@baylibre.com>
> 
>> This patch series can be found, along with the PRCI patch set
>> and the DT macro prerequisite patch, at:
>>
>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> nit: I only see this series in that branch, not any of the prerequisite
> patches you mentioned, which made me assume I could this series alone on
> top of v5.2-rc3, which worked just fine.
> 

I tried only this series on top of v5.2-rc3. Kernel boots file with DT 
updated via U-Boot. But networking didn't come up.

Do you have networking up after the boot? If yes, can you please share 
the config.

> Kevin
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 


-- 
Regards,
Atish

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-06 23:15     ` Atish Patra
  0 siblings, 0 replies; 55+ messages in thread
From: Atish Patra @ 2019-06-06 23:15 UTC (permalink / raw)
  To: Kevin Hilman, Paul Walmsley, linux-kernel, linux-riscv

On 6/5/19 10:37 AM, Kevin Hilman wrote:
> Hi Paul,
> 
> Paul Walmsley <paul.walmsley@sifive.com> writes:
> 
>> Add support for building flattened DT files from DT source files under
>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>> architectures.  Start our board support by adding initial support for
>> the SiFive FU540 SoC and the first development board that uses it, the
>> SiFive HiFive Unleashed A00.
>>
>> This third version of the patch set adds I2C data for the chip,
>> incorporates all remaining changes that riscv-pk was making
>> automatically, and addresses a comment from Rob Herring
>> <robh@kernel.org>.
>>
>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>> BBL and open-source FSBL, with modifications to pass in the DTB
>> file generated by these patches.
> 
> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> OpenSBI + mainline u-boot (master branch as of today).
> 
> Tested-by: Kevin Hilman <khilman@baylibre.com>
> 
>> This patch series can be found, along with the PRCI patch set
>> and the DT macro prerequisite patch, at:
>>
>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> nit: I only see this series in that branch, not any of the prerequisite
> patches you mentioned, which made me assume I could this series alone on
> top of v5.2-rc3, which worked just fine.
> 

I tried only this series on top of v5.2-rc3. Kernel boots file with DT 
updated via U-Boot. But networking didn't come up.

Do you have networking up after the boot? If yes, can you please share 
the config.

> Kevin
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 


-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-04 14:37     ` Loys Ollivier
@ 2019-06-07  5:12       ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:12 UTC (permalink / raw)
  To: Loys Ollivier
  Cc: linux-kernel, linux-riscv, Paul Walmsley, Palmer Dabbelt, Albert Ou

On Tue, 4 Jun 2019, Loys Ollivier wrote:

> Always build it ?
> Any particular reason to drop ARCH_SIFIVE ?

Palmer had some reservations about it, so I dropped it for now.  But then 
as I was thinking about it, I remembered that I also had some reservations 
about it, years ago: that everyone should use CONFIG_SOC_* for this, 
rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for 
CPU architectures.

If you agree, would you like to send a followup series, based on the DT 
patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

Thanks for the comment,

- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-07  5:12       ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:12 UTC (permalink / raw)
  To: Loys Ollivier
  Cc: linux-riscv, Paul Walmsley, Palmer Dabbelt, linux-kernel, Albert Ou

On Tue, 4 Jun 2019, Loys Ollivier wrote:

> Always build it ?
> Any particular reason to drop ARCH_SIFIVE ?

Palmer had some reservations about it, so I dropped it for now.  But then 
as I was thinking about it, I remembered that I also had some reservations 
about it, years ago: that everyone should use CONFIG_SOC_* for this, 
rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for 
CPU architectures.

If you agree, would you like to send a followup series, based on the DT 
patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

Thanks for the comment,

- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-04 14:31   ` Loys Ollivier
@ 2019-06-07  5:14     ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:14 UTC (permalink / raw)
  To: Loys Ollivier; +Cc: linux-kernel, linux-riscv

On Tue, 4 Jun 2019, Loys Ollivier wrote:

> On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> > Add support for building flattened DT files from DT source files under
> > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > architectures.  Start our board support by adding initial support for
> > the SiFive FU540 SoC and the first development board that uses it, the
> > SiFive HiFive Unleashed A00.
> >
> > This third version of the patch set adds I2C data for the chip,
> > incorporates all remaining changes that riscv-pk was making
> > automatically, and addresses a comment from Rob Herring
> > <robh@kernel.org>.
> >
> > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> > BBL and open-source FSBL, with modifications to pass in the DTB
> > file generated by these patches.
> >
> > This patch series can be found, along with the PRCI patch set
> > and the DT macro prerequisite patch, at:
> >
> > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed.
> Tested-by: Loys Ollivier <lollivier@baylibre.com>

Thanks very much for your testing!


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-07  5:14     ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:14 UTC (permalink / raw)
  To: Loys Ollivier; +Cc: linux-riscv, linux-kernel

On Tue, 4 Jun 2019, Loys Ollivier wrote:

> On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> > Add support for building flattened DT files from DT source files under
> > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > architectures.  Start our board support by adding initial support for
> > the SiFive FU540 SoC and the first development board that uses it, the
> > SiFive HiFive Unleashed A00.
> >
> > This third version of the patch set adds I2C data for the chip,
> > incorporates all remaining changes that riscv-pk was making
> > automatically, and addresses a comment from Rob Herring
> > <robh@kernel.org>.
> >
> > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> > BBL and open-source FSBL, with modifications to pass in the DTB
> > file generated by these patches.
> >
> > This patch series can be found, along with the PRCI patch set
> > and the DT macro prerequisite patch, at:
> >
> > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> Tested patch 1, 4 and 5 using FSBL + OpenSBI + U-Boot on HiFive Unleashed.
> Tested-by: Loys Ollivier <lollivier@baylibre.com>

Thanks very much for your testing!


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-05 17:36   ` Kevin Hilman
@ 2019-06-07  5:18     ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:18 UTC (permalink / raw)
  To: Kevin Hilman; +Cc: linux-kernel, linux-riscv

Hi Kevin,

On Wed, 5 Jun 2019, Kevin Hilman wrote:

> Paul Walmsley <paul.walmsley@sifive.com> writes:
> 
> > Add support for building flattened DT files from DT source files under
> > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > architectures.  Start our board support by adding initial support for
> > the SiFive FU540 SoC and the first development board that uses it, the
> > SiFive HiFive Unleashed A00.
> 
> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> OpenSBI + mainline u-boot (master branch as of today).
> 
> Tested-by: Kevin Hilman <khilman@baylibre.com>

Thanks very much!

> > This patch series can be found, along with the PRCI patch set
> > and the DT macro prerequisite patch, at:
> >
> > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> nit: I only see this series in that branch, not any of the prerequisite
> patches you mentioned, which made me assume I could this series alone on
> top of v5.2-rc3, which worked just fine.

Yep, just forgot to drop that part of the sentence from the series 
description.  Those prerequisite patches were already merged.


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-07  5:18     ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-07  5:18 UTC (permalink / raw)
  To: Kevin Hilman; +Cc: linux-riscv, linux-kernel

Hi Kevin,

On Wed, 5 Jun 2019, Kevin Hilman wrote:

> Paul Walmsley <paul.walmsley@sifive.com> writes:
> 
> > Add support for building flattened DT files from DT source files under
> > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > architectures.  Start our board support by adding initial support for
> > the SiFive FU540 SoC and the first development board that uses it, the
> > SiFive HiFive Unleashed A00.
> 
> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> OpenSBI + mainline u-boot (master branch as of today).
> 
> Tested-by: Kevin Hilman <khilman@baylibre.com>

Thanks very much!

> > This patch series can be found, along with the PRCI patch set
> > and the DT macro prerequisite patch, at:
> >
> > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> 
> nit: I only see this series in that branch, not any of the prerequisite
> patches you mentioned, which made me assume I could this series alone on
> top of v5.2-rc3, which worked just fine.

Yep, just forgot to drop that part of the sentence from the series 
description.  Those prerequisite patches were already merged.


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-07  5:12       ` Paul Walmsley
@ 2019-06-07  9:49         ` Loys Ollivier
  -1 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-07  9:49 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: linux-kernel, linux-riscv, Paul Walmsley, Palmer Dabbelt, Albert Ou

On Thu 06 Jun 2019 at 22:12, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> On Tue, 4 Jun 2019, Loys Ollivier wrote:
>
>> Always build it ?
>> Any particular reason to drop ARCH_SIFIVE ?
>
> Palmer had some reservations about it, so I dropped it for now.  But then 
> as I was thinking about it, I remembered that I also had some reservations 
> about it, years ago: that everyone should use CONFIG_SOC_* for this, 
> rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for 
> CPU architectures.

Agree on the CONFIG_SOC.

>
> If you agree, would you like to send a followup series, based on the DT 
> patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

Sure, I'd be glad to follow up on that. I'll send a followup series to
start a discussion.

--
Loys

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-07  9:49         ` Loys Ollivier
  0 siblings, 0 replies; 55+ messages in thread
From: Loys Ollivier @ 2019-06-07  9:49 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: linux-riscv, Paul Walmsley, Palmer Dabbelt, linux-kernel, Albert Ou

On Thu 06 Jun 2019 at 22:12, Paul Walmsley <paul.walmsley@sifive.com> wrote:

> On Tue, 4 Jun 2019, Loys Ollivier wrote:
>
>> Always build it ?
>> Any particular reason to drop ARCH_SIFIVE ?
>
> Palmer had some reservations about it, so I dropped it for now.  But then 
> as I was thinking about it, I remembered that I also had some reservations 
> about it, years ago: that everyone should use CONFIG_SOC_* for this, 
> rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for 
> CPU architectures.

Agree on the CONFIG_SOC.

>
> If you agree, would you like to send a followup series, based on the DT 
> patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

Sure, I'd be glad to follow up on that. I'll send a followup series to
start a discussion.

--
Loys

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-06 23:15     ` Atish Patra
@ 2019-06-07 16:51       ` Kevin Hilman
  -1 siblings, 0 replies; 55+ messages in thread
From: Kevin Hilman @ 2019-06-07 16:51 UTC (permalink / raw)
  To: Atish Patra, Paul Walmsley, linux-kernel, linux-riscv

Atish Patra <atish.patra@wdc.com> writes:

> On 6/5/19 10:37 AM, Kevin Hilman wrote:
>> Hi Paul,
>> 
>> Paul Walmsley <paul.walmsley@sifive.com> writes:
>> 
>>> Add support for building flattened DT files from DT source files under
>>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>>> architectures.  Start our board support by adding initial support for
>>> the SiFive FU540 SoC and the first development board that uses it, the
>>> SiFive HiFive Unleashed A00.
>>>
>>> This third version of the patch set adds I2C data for the chip,
>>> incorporates all remaining changes that riscv-pk was making
>>> automatically, and addresses a comment from Rob Herring
>>> <robh@kernel.org>.
>>>
>>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>>> BBL and open-source FSBL, with modifications to pass in the DTB
>>> file generated by these patches.
>> 
>> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
>> OpenSBI + mainline u-boot (master branch as of today).
>> 
>> Tested-by: Kevin Hilman <khilman@baylibre.com>
>> 
>>> This patch series can be found, along with the PRCI patch set
>>> and the DT macro prerequisite patch, at:
>>>
>>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>> 
>> nit: I only see this series in that branch, not any of the prerequisite
>> patches you mentioned, which made me assume I could this series alone on
>> top of v5.2-rc3, which worked just fine.
>> 
>
> I tried only this series on top of v5.2-rc3. Kernel boots file with DT 
> updated via U-Boot. But networking didn't come up.
>
> Do you have networking up after the boot? If yes, can you please share 
> the config.

I didn't test networking from the kernel initially, but looking now, I
do not have networking come up in the kernel either.

Kevin

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-07 16:51       ` Kevin Hilman
  0 siblings, 0 replies; 55+ messages in thread
From: Kevin Hilman @ 2019-06-07 16:51 UTC (permalink / raw)
  To: Atish Patra, Paul Walmsley, linux-kernel, linux-riscv

Atish Patra <atish.patra@wdc.com> writes:

> On 6/5/19 10:37 AM, Kevin Hilman wrote:
>> Hi Paul,
>> 
>> Paul Walmsley <paul.walmsley@sifive.com> writes:
>> 
>>> Add support for building flattened DT files from DT source files under
>>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>>> architectures.  Start our board support by adding initial support for
>>> the SiFive FU540 SoC and the first development board that uses it, the
>>> SiFive HiFive Unleashed A00.
>>>
>>> This third version of the patch set adds I2C data for the chip,
>>> incorporates all remaining changes that riscv-pk was making
>>> automatically, and addresses a comment from Rob Herring
>>> <robh@kernel.org>.
>>>
>>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>>> BBL and open-source FSBL, with modifications to pass in the DTB
>>> file generated by these patches.
>> 
>> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
>> OpenSBI + mainline u-boot (master branch as of today).
>> 
>> Tested-by: Kevin Hilman <khilman@baylibre.com>
>> 
>>> This patch series can be found, along with the PRCI patch set
>>> and the DT macro prerequisite patch, at:
>>>
>>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>> 
>> nit: I only see this series in that branch, not any of the prerequisite
>> patches you mentioned, which made me assume I could this series alone on
>> top of v5.2-rc3, which worked just fine.
>> 
>
> I tried only this series on top of v5.2-rc3. Kernel boots file with DT 
> updated via U-Boot. But networking didn't come up.
>
> Do you have networking up after the boot? If yes, can you please share 
> the config.

I didn't test networking from the kernel initially, but looking now, I
do not have networking come up in the kernel either.

Kevin

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-07 16:51       ` Kevin Hilman
@ 2019-06-07 17:58         ` Atish Patra
  -1 siblings, 0 replies; 55+ messages in thread
From: Atish Patra @ 2019-06-07 17:58 UTC (permalink / raw)
  To: Kevin Hilman, Paul Walmsley, linux-kernel, linux-riscv

On 6/7/19 9:52 AM, Kevin Hilman wrote:
> Atish Patra <atish.patra@wdc.com> writes:
> 
>> On 6/5/19 10:37 AM, Kevin Hilman wrote:
>>> Hi Paul,
>>>
>>> Paul Walmsley <paul.walmsley@sifive.com> writes:
>>>
>>>> Add support for building flattened DT files from DT source files under
>>>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>>>> architectures.  Start our board support by adding initial support for
>>>> the SiFive FU540 SoC and the first development board that uses it, the
>>>> SiFive HiFive Unleashed A00.
>>>>
>>>> This third version of the patch set adds I2C data for the chip,
>>>> incorporates all remaining changes that riscv-pk was making
>>>> automatically, and addresses a comment from Rob Herring
>>>> <robh@kernel.org>.
>>>>
>>>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>>>> BBL and open-source FSBL, with modifications to pass in the DTB
>>>> file generated by these patches.
>>>
>>> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
>>> OpenSBI + mainline u-boot (master branch as of today).
>>>
>>> Tested-by: Kevin Hilman <khilman@baylibre.com>
>>>
>>>> This patch series can be found, along with the PRCI patch set
>>>> and the DT macro prerequisite patch, at:
>>>>
>>>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>>>
>>> nit: I only see this series in that branch, not any of the prerequisite
>>> patches you mentioned, which made me assume I could this series alone on
>>> top of v5.2-rc3, which worked just fine.
>>>
>>
>> I tried only this series on top of v5.2-rc3. Kernel boots file with DT
>> updated via U-Boot. But networking didn't come up.
>>
>> Do you have networking up after the boot? If yes, can you please share
>> the config.
> 
> I didn't test networking from the kernel initially, but looking now, I
> do not have networking come up in the kernel either.
>

ok. I am not alone then :).

@Paul: Do you get networking up in your FSBL + BBL + Linux boot flow 
with the DT patch series ?

> Kevin
> 



-- 
Regards,
Atish

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-07 17:58         ` Atish Patra
  0 siblings, 0 replies; 55+ messages in thread
From: Atish Patra @ 2019-06-07 17:58 UTC (permalink / raw)
  To: Kevin Hilman, Paul Walmsley, linux-kernel, linux-riscv

On 6/7/19 9:52 AM, Kevin Hilman wrote:
> Atish Patra <atish.patra@wdc.com> writes:
> 
>> On 6/5/19 10:37 AM, Kevin Hilman wrote:
>>> Hi Paul,
>>>
>>> Paul Walmsley <paul.walmsley@sifive.com> writes:
>>>
>>>> Add support for building flattened DT files from DT source files under
>>>> arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
>>>> architectures.  Start our board support by adding initial support for
>>>> the SiFive FU540 SoC and the first development board that uses it, the
>>>> SiFive HiFive Unleashed A00.
>>>>
>>>> This third version of the patch set adds I2C data for the chip,
>>>> incorporates all remaining changes that riscv-pk was making
>>>> automatically, and addresses a comment from Rob Herring
>>>> <robh@kernel.org>.
>>>>
>>>> Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
>>>> BBL and open-source FSBL, with modifications to pass in the DTB
>>>> file generated by these patches.
>>>
>>> Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
>>> OpenSBI + mainline u-boot (master branch as of today).
>>>
>>> Tested-by: Kevin Hilman <khilman@baylibre.com>
>>>
>>>> This patch series can be found, along with the PRCI patch set
>>>> and the DT macro prerequisite patch, at:
>>>>
>>>> https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
>>>
>>> nit: I only see this series in that branch, not any of the prerequisite
>>> patches you mentioned, which made me assume I could this series alone on
>>> top of v5.2-rc3, which worked just fine.
>>>
>>
>> I tried only this series on top of v5.2-rc3. Kernel boots file with DT
>> updated via U-Boot. But networking didn't come up.
>>
>> Do you have networking up after the boot? If yes, can you please share
>> the config.
> 
> I didn't test networking from the kernel initially, but looking now, I
> do not have networking come up in the kernel either.
>

ok. I am not alone then :).

@Paul: Do you get networking up in your FSBL + BBL + Linux boot flow 
with the DT patch series ?

> Kevin
> 



-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
  2019-06-07 17:58         ` Atish Patra
@ 2019-06-07 20:55           ` Auer, Lukas
  -1 siblings, 0 replies; 55+ messages in thread
From: Auer, Lukas @ 2019-06-07 20:55 UTC (permalink / raw)
  To: paul.walmsley, linux-riscv, atish.patra, linux-kernel, khilman

On Fri, 2019-06-07 at 10:58 -0700, Atish Patra wrote:
> On 6/7/19 9:52 AM, Kevin Hilman wrote:
> > Atish Patra <atish.patra@wdc.com> writes:
> > 
> > > On 6/5/19 10:37 AM, Kevin Hilman wrote:
> > > > Hi Paul,
> > > > 
> > > > Paul Walmsley <paul.walmsley@sifive.com> writes:
> > > > 
> > > > > Add support for building flattened DT files from DT source files under
> > > > > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > > > > architectures.  Start our board support by adding initial support for
> > > > > the SiFive FU540 SoC and the first development board that uses it, the
> > > > > SiFive HiFive Unleashed A00.
> > > > > 
> > > > > This third version of the patch set adds I2C data for the chip,
> > > > > incorporates all remaining changes that riscv-pk was making
> > > > > automatically, and addresses a comment from Rob Herring
> > > > > <robh@kernel.org>.
> > > > > 
> > > > > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> > > > > BBL and open-source FSBL, with modifications to pass in the DTB
> > > > > file generated by these patches.
> > > > 
> > > > Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> > > > OpenSBI + mainline u-boot (master branch as of today).
> > > > 
> > > > Tested-by: Kevin Hilman <khilman@baylibre.com>
> > > > 
> > > > > This patch series can be found, along with the PRCI patch set
> > > > > and the DT macro prerequisite patch, at:
> > > > > 
> > > > > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> > > > 
> > > > nit: I only see this series in that branch, not any of the prerequisite
> > > > patches you mentioned, which made me assume I could this series alone on
> > > > top of v5.2-rc3, which worked just fine.
> > > > 
> > > 
> > > I tried only this series on top of v5.2-rc3. Kernel boots file with DT
> > > updated via U-Boot. But networking didn't come up.
> > > 
> > > Do you have networking up after the boot? If yes, can you please share
> > > the config.
> > 
> > I didn't test networking from the kernel initially, but looking now, I
> > do not have networking come up in the kernel either.
> > 
> 
> ok. I am not alone then :).
> 
> @Paul: Do you get networking up in your FSBL + BBL + Linux boot flow 
> with the DT patch series ?
> 

There does not appear to be a device tree node for the ethernet
controller, which would be why networking is not coming up. U-Boot also
has to be updated to match the new device bindings introduced by the
ethernet controller patches currently on the mailing list [1].

Thanks,
Lukas

[1]: 
https://patchwork.kernel.org/project/linux-riscv/list/?series=121579

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-07 20:55           ` Auer, Lukas
  0 siblings, 0 replies; 55+ messages in thread
From: Auer, Lukas @ 2019-06-07 20:55 UTC (permalink / raw)
  To: paul.walmsley, linux-riscv, atish.patra, linux-kernel, khilman

On Fri, 2019-06-07 at 10:58 -0700, Atish Patra wrote:
> On 6/7/19 9:52 AM, Kevin Hilman wrote:
> > Atish Patra <atish.patra@wdc.com> writes:
> > 
> > > On 6/5/19 10:37 AM, Kevin Hilman wrote:
> > > > Hi Paul,
> > > > 
> > > > Paul Walmsley <paul.walmsley@sifive.com> writes:
> > > > 
> > > > > Add support for building flattened DT files from DT source files under
> > > > > arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
> > > > > architectures.  Start our board support by adding initial support for
> > > > > the SiFive FU540 SoC and the first development board that uses it, the
> > > > > SiFive HiFive Unleashed A00.
> > > > > 
> > > > > This third version of the patch set adds I2C data for the chip,
> > > > > incorporates all remaining changes that riscv-pk was making
> > > > > automatically, and addresses a comment from Rob Herring
> > > > > <robh@kernel.org>.
> > > > > 
> > > > > Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
> > > > > BBL and open-source FSBL, with modifications to pass in the DTB
> > > > > file generated by these patches.
> > > > 
> > > > Tested this series on top of v5.2-rc3 on HiFive Unleashed board using
> > > > OpenSBI + mainline u-boot (master branch as of today).
> > > > 
> > > > Tested-by: Kevin Hilman <khilman@baylibre.com>
> > > > 
> > > > > This patch series can be found, along with the PRCI patch set
> > > > > and the DT macro prerequisite patch, at:
> > > > > 
> > > > > https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
> > > > 
> > > > nit: I only see this series in that branch, not any of the prerequisite
> > > > patches you mentioned, which made me assume I could this series alone on
> > > > top of v5.2-rc3, which worked just fine.
> > > > 
> > > 
> > > I tried only this series on top of v5.2-rc3. Kernel boots file with DT
> > > updated via U-Boot. But networking didn't come up.
> > > 
> > > Do you have networking up after the boot? If yes, can you please share
> > > the config.
> > 
> > I didn't test networking from the kernel initially, but looking now, I
> > do not have networking come up in the kernel either.
> > 
> 
> ok. I am not alone then :).
> 
> @Paul: Do you get networking up in your FSBL + BBL + Linux boot flow 
> with the DT patch series ?
> 

There does not appear to be a device tree node for the ethernet
controller, which would be why networking is not coming up. U-Boot also
has to be updated to match the new device bindings introduced by the
ethernet controller patches currently on the mailing list [1].

Thanks,
Lukas

[1]: 
https://patchwork.kernel.org/project/linux-riscv/list/?series=121579
_______________________________________________
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^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-07  5:12       ` Paul Walmsley
@ 2019-06-08 17:56         ` Palmer Dabbelt
  -1 siblings, 0 replies; 55+ messages in thread
From: Palmer Dabbelt @ 2019-06-08 17:56 UTC (permalink / raw)
  To: Paul Walmsley; +Cc: lollivier, linux-kernel, linux-riscv, paul, aou

On Thu, 06 Jun 2019 22:12:05 PDT (-0700), Paul Walmsley wrote:
> On Tue, 4 Jun 2019, Loys Ollivier wrote:
>
>> Always build it ?
>> Any particular reason to drop ARCH_SIFIVE ?
>
> Palmer had some reservations about it, so I dropped it for now.  But then
> as I was thinking about it, I remembered that I also had some reservations
> about it, years ago: that everyone should use CONFIG_SOC_* for this,
> rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for
> CPU architectures.

Specifically my worry is that "ARCH_SIFIVE" makes it sound like we're adding
SiFive-specific architecture features, and we've been trying really hard to
make sure that the various bits of core software avoid boing vendor specific.
We've had suggestions of adding vendor-specific instructions to the Linux port
with those instructions being conditionally compiled under ARCH_$VENDOR, but
I'd rejected that under the "no vendor-specific stuff" argument.  As such it
doesn't seem fair to go add in an ARCH_SIFIVE for our vendor-specific stuff.

The SOC stuff will, of course, be vendor specific.  In this idealized world
SiFive's SOC support has nothing to do with RISC-V, but of course all of
SiFive's SOCs are RISC-V based so the separation is a bit of pedantry.  That
said, in this case I think getting the name right does make it slightly easier
to espouse this "one kernel can run on all RISC-V systems" philosophy.
Balancing the SiFive and RISC-V stuff can be a bit tricky, which is why I am
sometimes a bit pedantic about these sorts of things.

> If you agree, would you like to send a followup series, based on the DT
> patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

I'd be happy with something like that.  We'd also talked about this selecting
all the SiFive platform drivers.  It should, of course, be possible to select
multiple SOC vendors in a single kernel -- we don't have any other real
hardware right now, but maybe some sort of "CONFIG_SOC_RISCV_VIRT" would be a
good proof of concept?

> Thanks for the comment,
>
> - Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-08 17:56         ` Palmer Dabbelt
  0 siblings, 0 replies; 55+ messages in thread
From: Palmer Dabbelt @ 2019-06-08 17:56 UTC (permalink / raw)
  To: Paul Walmsley; +Cc: linux-riscv, lollivier, paul, linux-kernel, aou

On Thu, 06 Jun 2019 22:12:05 PDT (-0700), Paul Walmsley wrote:
> On Tue, 4 Jun 2019, Loys Ollivier wrote:
>
>> Always build it ?
>> Any particular reason to drop ARCH_SIFIVE ?
>
> Palmer had some reservations about it, so I dropped it for now.  But then
> as I was thinking about it, I remembered that I also had some reservations
> about it, years ago: that everyone should use CONFIG_SOC_* for this,
> rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for
> CPU architectures.

Specifically my worry is that "ARCH_SIFIVE" makes it sound like we're adding
SiFive-specific architecture features, and we've been trying really hard to
make sure that the various bits of core software avoid boing vendor specific.
We've had suggestions of adding vendor-specific instructions to the Linux port
with those instructions being conditionally compiled under ARCH_$VENDOR, but
I'd rejected that under the "no vendor-specific stuff" argument.  As such it
doesn't seem fair to go add in an ARCH_SIFIVE for our vendor-specific stuff.

The SOC stuff will, of course, be vendor specific.  In this idealized world
SiFive's SOC support has nothing to do with RISC-V, but of course all of
SiFive's SOCs are RISC-V based so the separation is a bit of pedantry.  That
said, in this case I think getting the name right does make it slightly easier
to espouse this "one kernel can run on all RISC-V systems" philosophy.
Balancing the SiFive and RISC-V stuff can be a bit tricky, which is why I am
sometimes a bit pedantic about these sorts of things.

> If you agree, would you like to send a followup series, based on the DT
> patches, to make the SiFive DT file builds depend on CONFIG_SOC_* instead?

I'd be happy with something like that.  We'd also talked about this selecting
all the SiFive platform drivers.  It should, of course, be possible to select
multiple SOC vendors in a single kernel -- we don't have any other real
hardware right now, but maybe some sort of "CONFIG_SOC_RISCV_VIRT" would be a
good proof of concept?

> Thanks for the comment,
>
> - Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-08 17:56         ` Palmer Dabbelt
@ 2019-06-09  5:50           ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-09  5:50 UTC (permalink / raw)
  To: Palmer Dabbelt; +Cc: lollivier, linux-kernel, linux-riscv, paul, aou

On Sat, 8 Jun 2019, Palmer Dabbelt wrote:

> On Thu, 06 Jun 2019 22:12:05 PDT (-0700), Paul Walmsley wrote:
> > On Tue, 4 Jun 2019, Loys Ollivier wrote:
> > 
> > > Always build it ?
> > > Any particular reason to drop ARCH_SIFIVE ?
> > 
> > Palmer had some reservations about it, so I dropped it for now.  But then
> > as I was thinking about it, I remembered that I also had some reservations
> > about it, years ago: that everyone should use CONFIG_SOC_* for this,
> > rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for
> > CPU architectures.
> 
> The SOC stuff will, of course, be vendor specific.  In this idealized world
> SiFive's SOC support has nothing to do with RISC-V, but of course all of
> SiFive's SOCs are RISC-V based so the separation is a bit of pedantry.  That
> said, in this case I think getting the name right does make it slightly easier
> to espouse this "one kernel can run on all RISC-V systems" philosophy.
> Balancing the SiFive and RISC-V stuff can be a bit tricky, which is why I am
> sometimes a bit pedantic about these sorts of things.

Once there are SoC variants that have different CPU cores, but with the 
remaining chip integration the same, I think it would make sense to move 
the CONFIG_SOC_ stuff out from ARM, RISC-V, etc., into something that's 
not CPU architecture-specific.  But for the time being, that seems 
premature.  Might as well have it be driven by an actual use-case.


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-09  5:50           ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-09  5:50 UTC (permalink / raw)
  To: Palmer Dabbelt; +Cc: linux-riscv, lollivier, paul, linux-kernel, aou

On Sat, 8 Jun 2019, Palmer Dabbelt wrote:

> On Thu, 06 Jun 2019 22:12:05 PDT (-0700), Paul Walmsley wrote:
> > On Tue, 4 Jun 2019, Loys Ollivier wrote:
> > 
> > > Always build it ?
> > > Any particular reason to drop ARCH_SIFIVE ?
> > 
> > Palmer had some reservations about it, so I dropped it for now.  But then
> > as I was thinking about it, I remembered that I also had some reservations
> > about it, years ago: that everyone should use CONFIG_SOC_* for this,
> > rather than CONFIG_ARCH.  CONFIG_ARCH_* seems better reserved for
> > CPU architectures.
> 
> The SOC stuff will, of course, be vendor specific.  In this idealized world
> SiFive's SOC support has nothing to do with RISC-V, but of course all of
> SiFive's SOCs are RISC-V based so the separation is a bit of pedantry.  That
> said, in this case I think getting the name right does make it slightly easier
> to espouse this "one kernel can run on all RISC-V systems" philosophy.
> Balancing the SiFive and RISC-V stuff can be a bit tricky, which is why I am
> sometimes a bit pedantic about these sorts of things.

Once there are SoC variants that have different CPU cores, but with the 
remaining chip integration the same, I think it would make sense to move 
the CONFIG_SOC_ stuff out from ARM, RISC-V, etc., into something that's 
not CPU architecture-specific.  But for the time being, that seems 
premature.  Might as well have it be driven by an actual use-case.


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
  2019-06-02  8:05   ` Paul Walmsley
  (?)
@ 2019-06-09  6:18     ` Antony Pavlov
  -1 siblings, 0 replies; 55+ messages in thread
From: Antony Pavlov @ 2019-06-09  6:18 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: linux-kernel, linux-riscv, Mark Rutland, devicetree,
	Paul Walmsley, Albert Ou, Palmer Dabbelt, Rob Herring

On Sun,  2 Jun 2019 01:05:00 -0700
Paul Walmsley <paul.walmsley@sifive.com> wrote:

Hi!

> Add initial board data for the SiFive HiFive Unleashed A00.
> 
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
> 
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
> 
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  arch/riscv/boot/dts/sifive/Makefile           |  2 +
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  | 67 +++++++++++++++++++
>  2 files changed, 69 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sifive/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> 
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..baaeef9efdcb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-y += hifive-unleashed-a00.dtb
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> new file mode 100644
> index 000000000000..1de4ea1577d5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"

You already have "/dts-v1/;" in the fu540-c000.dtsi file.

You can omit it in the hifive-unleashed-a00.dts file.

> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ		1000000
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SiFive HiFive Unleashed A00";
> +	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
> +
> +	chosen {
> +	};
> +
> +	cpus {
> +		timebase-frequency = <RTCCLK_FREQ>;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;
> +	};
> +
> +	soc {
> +	};
> +
> +	hfclk: hfclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <33333333>;
> +		clock-output-names = "hfclk";
> +	};
> +
> +	rtcclk: rtcclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <RTCCLK_FREQ>;
> +		clock-output-names = "rtcclk";
> +	};
> +};
> +
> +&qspi0 {
> +	flash@0 {
> +		compatible = "issi,is25wp256", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <50000000>;
> +		m25p,fast-read;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&qspi2 {
> +	status = "okay";
> +	mmc@0 {
> +		compatible = "mmc-spi-slot";
> +		reg = <0>;
> +		spi-max-frequency = <20000000>;
> +		voltage-ranges = <3300 3300>;
> +		disable-wp;
> +	};
> +};
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv


-- 
Best regards,
  Antony Pavlov

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-09  6:18     ` Antony Pavlov
  0 siblings, 0 replies; 55+ messages in thread
From: Antony Pavlov @ 2019-06-09  6:18 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, Rob Herring, linux-riscv

On Sun,  2 Jun 2019 01:05:00 -0700
Paul Walmsley <paul.walmsley@sifive.com> wrote:

Hi!

> Add initial board data for the SiFive HiFive Unleashed A00.
> 
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
> 
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
> 
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  arch/riscv/boot/dts/sifive/Makefile           |  2 +
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  | 67 +++++++++++++++++++
>  2 files changed, 69 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sifive/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> 
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..baaeef9efdcb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-y += hifive-unleashed-a00.dtb
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> new file mode 100644
> index 000000000000..1de4ea1577d5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"

You already have "/dts-v1/;" in the fu540-c000.dtsi file.

You can omit it in the hifive-unleashed-a00.dts file.

> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ		1000000
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SiFive HiFive Unleashed A00";
> +	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
> +
> +	chosen {
> +	};
> +
> +	cpus {
> +		timebase-frequency = <RTCCLK_FREQ>;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;
> +	};
> +
> +	soc {
> +	};
> +
> +	hfclk: hfclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <33333333>;
> +		clock-output-names = "hfclk";
> +	};
> +
> +	rtcclk: rtcclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <RTCCLK_FREQ>;
> +		clock-output-names = "rtcclk";
> +	};
> +};
> +
> +&qspi0 {
> +	flash@0 {
> +		compatible = "issi,is25wp256", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <50000000>;
> +		m25p,fast-read;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&qspi2 {
> +	status = "okay";
> +	mmc@0 {
> +		compatible = "mmc-spi-slot";
> +		reg = <0>;
> +		spi-max-frequency = <20000000>;
> +		voltage-ranges = <3300 3300>;
> +		disable-wp;
> +	};
> +};
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv


-- 
Best regards,
  Antony Pavlov

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-09  6:18     ` Antony Pavlov
  0 siblings, 0 replies; 55+ messages in thread
From: Antony Pavlov @ 2019-06-09  6:18 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, Rob Herring, linux-riscv

On Sun,  2 Jun 2019 01:05:00 -0700
Paul Walmsley <paul.walmsley@sifive.com> wrote:

Hi!

> Add initial board data for the SiFive HiFive Unleashed A00.
> 
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
> 
> This third version incorporates changes based on more comments from
> Rob Herring <robh+dt@kernel.org>.
> 
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  arch/riscv/boot/dts/sifive/Makefile           |  2 +
>  .../boot/dts/sifive/hifive-unleashed-a00.dts  | 67 +++++++++++++++++++
>  2 files changed, 69 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sifive/Makefile
>  create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> 
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..baaeef9efdcb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-y += hifive-unleashed-a00.dtb
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> new file mode 100644
> index 000000000000..1de4ea1577d5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"

You already have "/dts-v1/;" in the fu540-c000.dtsi file.

You can omit it in the hifive-unleashed-a00.dts file.

> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ		1000000
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SiFive HiFive Unleashed A00";
> +	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
> +
> +	chosen {
> +	};
> +
> +	cpus {
> +		timebase-frequency = <RTCCLK_FREQ>;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;
> +	};
> +
> +	soc {
> +	};
> +
> +	hfclk: hfclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <33333333>;
> +		clock-output-names = "hfclk";
> +	};
> +
> +	rtcclk: rtcclk {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <RTCCLK_FREQ>;
> +		clock-output-names = "rtcclk";
> +	};
> +};
> +
> +&qspi0 {
> +	flash@0 {
> +		compatible = "issi,is25wp256", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <50000000>;
> +		m25p,fast-read;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&qspi2 {
> +	status = "okay";
> +	mmc@0 {
> +		compatible = "mmc-spi-slot";
> +		reg = <0>;
> +		spi-max-frequency = <20000000>;
> +		voltage-ranges = <3300 3300>;
> +		disable-wp;
> +	};
> +};
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv


-- 
Best regards,
  Antony Pavlov

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
  2019-06-09  5:50           ` Paul Walmsley
@ 2019-06-09  7:49             ` Christoph Hellwig
  -1 siblings, 0 replies; 55+ messages in thread
From: Christoph Hellwig @ 2019-06-09  7:49 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: Palmer Dabbelt, linux-riscv, lollivier, paul, linux-kernel, aou

On Sat, Jun 08, 2019 at 10:50:14PM -0700, Paul Walmsley wrote:
> Once there are SoC variants that have different CPU cores, but with the 
> remaining chip integration the same, I think it would make sense to move 
> the CONFIG_SOC_ stuff out from ARM, RISC-V, etc., into something that's 
> not CPU architecture-specific.  But for the time being, that seems 
> premature.  Might as well have it be driven by an actual use-case.

We've already had a few SOC families with the same periphals glue and
either m68k/powerpc, powerpc/mips or mips/arm/arm64 CPUs, so this isn't
exactly new.  Not really sure the grouping adds that much value, though.

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-09  7:49             ` Christoph Hellwig
  0 siblings, 0 replies; 55+ messages in thread
From: Christoph Hellwig @ 2019-06-09  7:49 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: paul, aou, Palmer Dabbelt, linux-kernel, linux-riscv, lollivier

On Sat, Jun 08, 2019 at 10:50:14PM -0700, Paul Walmsley wrote:
> Once there are SoC variants that have different CPU cores, but with the 
> remaining chip integration the same, I think it would make sense to move 
> the CONFIG_SOC_ stuff out from ARM, RISC-V, etc., into something that's 
> not CPU architecture-specific.  But for the time being, that seems 
> premature.  Might as well have it be driven by an actual use-case.

We've already had a few SOC families with the same periphals glue and
either m68k/powerpc, powerpc/mips or mips/arm/arm64 CPUs, so this isn't
exactly new.  Not really sure the grouping adds that much value, though.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
  2019-06-02  8:04   ` Paul Walmsley
@ 2019-06-10 21:44     ` Rob Herring
  -1 siblings, 0 replies; 55+ messages in thread
From: Rob Herring @ 2019-06-10 21:44 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: linux-kernel, linux-riscv, Paul Walmsley, Mark Rutland,
	Palmer Dabbelt, Albert Ou, devicetree

On Sun, Jun 2, 2019 at 2:05 AM Paul Walmsley <paul.walmsley@sifive.com> wrote:
>
> Add YAML DT binding documentation for the SiFive FU540 SoC.  This
> SoC is documented at:
>
>     https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.
>
> This second version incorporates review feedback from Rob Herring
> <robh@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
>  MAINTAINERS                                   |  9 +++++++
>  2 files changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml

Reviewed-by: Rob Herring <robh@kernel.org>

>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
> new file mode 100644
> index 000000000000..ce7ca191789e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
> @@ -0,0 +1,25 @@
> +# SPDX-License-Identifier: GPL-2.0

Note that the preference for new bindings (or old ones you have
ownership of) is to dual license GPL-2.0 and BSD-2-Clause.

Rob

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
@ 2019-06-10 21:44     ` Rob Herring
  0 siblings, 0 replies; 55+ messages in thread
From: Rob Herring @ 2019-06-10 21:44 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, linux-riscv

On Sun, Jun 2, 2019 at 2:05 AM Paul Walmsley <paul.walmsley@sifive.com> wrote:
>
> Add YAML DT binding documentation for the SiFive FU540 SoC.  This
> SoC is documented at:
>
>     https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.
>
> This second version incorporates review feedback from Rob Herring
> <robh@kernel.org>.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
>  MAINTAINERS                                   |  9 +++++++
>  2 files changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml

Reviewed-by: Rob Herring <robh@kernel.org>

>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
> new file mode 100644
> index 000000000000..ce7ca191789e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
> @@ -0,0 +1,25 @@
> +# SPDX-License-Identifier: GPL-2.0

Note that the preference for new bindings (or old ones you have
ownership of) is to dual license GPL-2.0 and BSD-2-Clause.

Rob

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
  2019-06-09  6:18     ` Antony Pavlov
  (?)
@ 2019-06-16 18:36       ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-16 18:36 UTC (permalink / raw)
  To: Antony Pavlov
  Cc: linux-kernel, linux-riscv, Mark Rutland, devicetree,
	Paul Walmsley, Albert Ou, Palmer Dabbelt, Rob Herring

On Sun, 9 Jun 2019, Antony Pavlov wrote:

> On Sun,  2 Jun 2019 01:05:00 -0700
> Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> Hi!
> 
> > Add initial board data for the SiFive HiFive Unleashed A00.

...

> > new file mode 100644
> > index 000000000000..1de4ea1577d5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2018-2019 SiFive, Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "fu540-c000.dtsi"
> 
> You already have "/dts-v1/;" in the fu540-c000.dtsi file.
> 
> You can omit it in the hifive-unleashed-a00.dts file.

Thanks for the comment.  Dropped the line, per your suggestion.


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-16 18:36       ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-16 18:36 UTC (permalink / raw)
  To: Antony Pavlov
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, Rob Herring, linux-riscv

On Sun, 9 Jun 2019, Antony Pavlov wrote:

> On Sun,  2 Jun 2019 01:05:00 -0700
> Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> Hi!
> 
> > Add initial board data for the SiFive HiFive Unleashed A00.

...

> > new file mode 100644
> > index 000000000000..1de4ea1577d5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2018-2019 SiFive, Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "fu540-c000.dtsi"
> 
> You already have "/dts-v1/;" in the fu540-c000.dtsi file.
> 
> You can omit it in the hifive-unleashed-a00.dts file.

Thanks for the comment.  Dropped the line, per your suggestion.


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed
@ 2019-06-16 18:36       ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-16 18:36 UTC (permalink / raw)
  To: Antony Pavlov
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, Rob Herring, linux-riscv

On Sun, 9 Jun 2019, Antony Pavlov wrote:

> On Sun,  2 Jun 2019 01:05:00 -0700
> Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> Hi!
> 
> > Add initial board data for the SiFive HiFive Unleashed A00.

...

> > new file mode 100644
> > index 000000000000..1de4ea1577d5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2018-2019 SiFive, Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "fu540-c000.dtsi"
> 
> You already have "/dts-v1/;" in the fu540-c000.dtsi file.
> 
> You can omit it in the hifive-unleashed-a00.dts file.

Thanks for the comment.  Dropped the line, per your suggestion.


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
  2019-06-10 21:44     ` Rob Herring
@ 2019-06-16 18:39       ` Paul Walmsley
  -1 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-16 18:39 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-kernel, linux-riscv, Paul Walmsley, Mark Rutland,
	Palmer Dabbelt, Albert Ou, devicetree

On Mon, 10 Jun 2019, Rob Herring wrote:

> On Sun, Jun 2, 2019 at 2:05 AM Paul Walmsley <paul.walmsley@sifive.com> wrote:
> >
> > Add YAML DT binding documentation for the SiFive FU540 SoC. 

...

> > ---
> >  .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
> >  MAINTAINERS                                   |  9 +++++++
> >  2 files changed, 34 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Thanks.

> > diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
> > new file mode 100644
> > index 000000000000..ce7ca191789e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
> > @@ -0,0 +1,25 @@
> > +# SPDX-License-Identifier: GPL-2.0
> 
> Note that the preference for new bindings (or old ones you have
> ownership of) is to dual license GPL-2.0 and BSD-2-Clause.

Changed to "(GPL-2.0 OR MIT)" - hope that's OK.


- Paul

^ permalink raw reply	[flat|nested] 55+ messages in thread

* Re: [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
@ 2019-06-16 18:39       ` Paul Walmsley
  0 siblings, 0 replies; 55+ messages in thread
From: Paul Walmsley @ 2019-06-16 18:39 UTC (permalink / raw)
  To: Rob Herring
  Cc: Mark Rutland, devicetree, Paul Walmsley, Albert Ou,
	Palmer Dabbelt, linux-kernel, linux-riscv

On Mon, 10 Jun 2019, Rob Herring wrote:

> On Sun, Jun 2, 2019 at 2:05 AM Paul Walmsley <paul.walmsley@sifive.com> wrote:
> >
> > Add YAML DT binding documentation for the SiFive FU540 SoC. 

...

> > ---
> >  .../devicetree/bindings/riscv/sifive.yaml     | 25 +++++++++++++++++++
> >  MAINTAINERS                                   |  9 +++++++
> >  2 files changed, 34 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Thanks.

> > diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml
> > new file mode 100644
> > index 000000000000..ce7ca191789e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml
> > @@ -0,0 +1,25 @@
> > +# SPDX-License-Identifier: GPL-2.0
> 
> Note that the preference for new bindings (or old ones you have
> ownership of) is to dual license GPL-2.0 and BSD-2-Clause.

Changed to "(GPL-2.0 OR MIT)" - hope that's OK.


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 55+ messages in thread

end of thread, other threads:[~2019-06-16 18:39 UTC | newest]

Thread overview: 55+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-02  8:04 [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Paul Walmsley
2019-06-02  8:04 ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-04 14:37   ` Loys Ollivier
2019-06-04 14:37     ` Loys Ollivier
2019-06-07  5:12     ` Paul Walmsley
2019-06-07  5:12       ` Paul Walmsley
2019-06-07  9:49       ` Loys Ollivier
2019-06-07  9:49         ` Loys Ollivier
2019-06-08 17:56       ` Palmer Dabbelt
2019-06-08 17:56         ` Palmer Dabbelt
2019-06-09  5:50         ` Paul Walmsley
2019-06-09  5:50           ` Paul Walmsley
2019-06-09  7:49           ` Christoph Hellwig
2019-06-09  7:49             ` Christoph Hellwig
2019-06-02  8:04 ` [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-10 21:44   ` Rob Herring
2019-06-10 21:44     ` Rob Herring
2019-06-16 18:39     ` Paul Walmsley
2019-06-16 18:39       ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-02  8:04 ` [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2019-06-02  8:04   ` Paul Walmsley
2019-06-04 14:38   ` Loys Ollivier
2019-06-04 14:38     ` Loys Ollivier
2019-06-02  8:05 ` [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2019-06-02  8:05   ` Paul Walmsley
2019-06-04 14:41   ` Loys Ollivier
2019-06-04 14:41     ` Loys Ollivier
2019-06-09  6:18   ` Antony Pavlov
2019-06-09  6:18     ` Antony Pavlov
2019-06-09  6:18     ` Antony Pavlov
2019-06-16 18:36     ` Paul Walmsley
2019-06-16 18:36       ` Paul Walmsley
2019-06-16 18:36       ` Paul Walmsley
2019-06-04 14:31 ` [PATCH v3 0/5] arch: riscv: add board and SoC DT file support Loys Ollivier
2019-06-04 14:31   ` Loys Ollivier
2019-06-07  5:14   ` Paul Walmsley
2019-06-07  5:14     ` Paul Walmsley
2019-06-05 17:36 ` Kevin Hilman
2019-06-05 17:36   ` Kevin Hilman
2019-06-06 23:15   ` Atish Patra
2019-06-06 23:15     ` Atish Patra
2019-06-07 16:51     ` Kevin Hilman
2019-06-07 16:51       ` Kevin Hilman
2019-06-07 17:58       ` Atish Patra
2019-06-07 17:58         ` Atish Patra
2019-06-07 20:55         ` Auer, Lukas
2019-06-07 20:55           ` Auer, Lukas
2019-06-07  5:18   ` Paul Walmsley
2019-06-07  5:18     ` Paul Walmsley

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