From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D46D2C28CC6 for ; Mon, 3 Jun 2019 16:18:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AE74924BAC for ; Mon, 3 Jun 2019 16:18:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728800AbfFCQSS (ORCPT ); Mon, 3 Jun 2019 12:18:18 -0400 Received: from mga02.intel.com ([134.134.136.20]:31738 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726521AbfFCQSS (ORCPT ); Mon, 3 Jun 2019 12:18:18 -0400 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jun 2019 09:18:18 -0700 X-ExtLoop1: 1 Received: from sjchrist-coffee.jf.intel.com (HELO linux.intel.com) ([10.54.74.36]) by orsmga006.jf.intel.com with ESMTP; 03 Jun 2019 09:18:17 -0700 Date: Mon, 3 Jun 2019 09:18:17 -0700 From: Sean Christopherson To: Jiri Kosina Cc: Andy Lutomirski , Andy Lutomirski , "Rafael J. Wysocki" , Josh Poimboeuf , "Rafael J. Wysocki" , Thomas Gleixner , the arch/x86 maintainers , Pavel Machek , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Peter Zijlstra , Linux PM , Linux Kernel Mailing List Subject: Re: [PATCH v4] x86/power: Fix 'nosmt' vs. hibernation triple fault during resume Message-ID: <20190603161817.GD13384@linux.intel.com> References: <5564116.e9OFvgDRbB@kreacher> <98E57C7E-24E2-4EB8-A14E-FCA80316F812@amacapital.net> <20190603142330.GA13384@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 03, 2019 at 05:24:26PM +0200, Jiri Kosina wrote: > On Mon, 3 Jun 2019, Sean Christopherson wrote: > > > For P6 and later, i.e. all modern CPUs, Intel processors go straight to > > halted state and don't fetch/decode the HLT instruction. > > That'd be a rather relieving fact actually. Do you happen to know if this > is stated in some Intel documentation and we've just overlooked it, or > whether it's rather an information that's being carried over from > generation to generation by whispering through grapevine? I highly doubt it's officially stated anywhere. Intel's approach to this type of micro-architecture specific behavior is (usually) to word the SDM in such a way that both approaches are legal. E.g. a 1993 version of the SDM says "Returns to interrupted HLT instruction", whereas in 1995, which just so happens to coincide with the introduction of the P6 architecture, the SDM started saying "Returns to HALT state" and added the blurb about "will generate a memory access to fetch the HLT instruction (if it is not in the internal cache)" so that the old behavior is still legal. All that being said, the "straight to HALT" behavior is now the de facto standard since lots of people will yell loudly if it changes.