From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D80AC04AB5 for ; Mon, 3 Jun 2019 23:27:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B07224321 for ; Mon, 3 Jun 2019 23:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726547AbfFCX1r (ORCPT ); Mon, 3 Jun 2019 19:27:47 -0400 Received: from mga04.intel.com ([192.55.52.120]:11876 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726179AbfFCX1q (ORCPT ); Mon, 3 Jun 2019 19:27:46 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jun 2019 16:27:46 -0700 X-ExtLoop1: 1 Received: from jbrandeb-mobl2.amr.corp.intel.com (HELO localhost) ([10.254.84.131]) by fmsmga007.fm.intel.com with ESMTP; 03 Jun 2019 16:27:46 -0700 Date: Mon, 3 Jun 2019 16:27:45 -0700 From: Jesse Brandeburg To: Robert Hancock Cc: , jesse.brandeburg@intel.com Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver Message-ID: <20190603162745.00007313@intel.com> In-Reply-To: <1559603524-18288-1-git-send-email-hancock@sedsystems.ca> References: <1559603524-18288-1-git-send-email-hancock@sedsystems.ca> X-Mailer: Claws Mail 3.12.0 (GTK+ 2.24.28; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Mon, 3 Jun 2019 17:12:04 -0600 Robert Hancock wrote: > This adds a driver for the PHY device implemented in the Xilinx PCS/PMA > Core logic. This is mostly a generic gigabit PHY, except that the > features are explicitly set because the PHY wrongly indicates it has no > extended status register when it actually does. > > This version is a simplified version of the GPL 2+ version from the > Xilinx kernel tree. > > Signed-off-by: Robert Hancock > --- > > Differences from v1: > -Removed unnecessary config_init method > -Added comment to explain why features are explicitly set > > drivers/net/phy/Kconfig | 6 ++++++ > drivers/net/phy/Makefile | 1 + > drivers/net/phy/xilinx.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 58 insertions(+) > create mode 100644 drivers/net/phy/xilinx.c > Seems fine. Reviewed-by: Jesse Brandeburg