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[100.0.197.103]) by smtp.gmail.com with ESMTPSA id d123sm3655531qkb.94.2019.06.04.19.27.10 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 04 Jun 2019 19:27:11 -0700 (PDT) Date: Tue, 4 Jun 2019 22:27:09 -0400 From: "Michael S. Tsirkin" To: Alex Williamson Message-ID: <20190604222700-mutt-send-email-mst@kernel.org> References: <155968619555.19319.478535697621079640.stgit@gimli.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <155968619555.19319.478535697621079640.stgit@gimli.home> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.222.195 Subject: Re: [Qemu-devel] [PATCH v2] [for 4.0.1] q35: Revert to kernel irqchip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, qemu-stable@nongnu.org, pbonzini@redhat.com, mdroth@linux.vnet.ibm.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jun 04, 2019 at 04:12:24PM -0600, Alex Williamson wrote: > Backport of QEMU v4.1 commit for stable v4.0.1 release > > commit c87759ce876a7a0b17c2bf4f0b964bd51f0ee871 > Author: Alex Williamson > Date: Tue May 14 14:14:41 2019 -0600 > > q35: Revert to kernel irqchip > > Commit b2fc91db8447 ("q35: set split kernel irqchip as default") changed > the default for the pc-q35-4.0 machine type to use split irqchip, which > turned out to have disasterous effects on vfio-pci INTx support. KVM > resampling irqfds are registered for handling these interrupts, but > these are non-functional in split irqchip mode. We can't simply test > for split irqchip in QEMU as userspace handling of this interrupt is a > significant performance regression versus KVM handling (GeForce GPUs > assigned to Windows VMs are non-functional without forcing MSI mode or > re-enabling kernel irqchip). > > The resolution is to revert the change in default irqchip mode in the > pc-q35-4.1 machine and create a pc-q35-4.0.1 machine for the 4.0-stable > branch. The qemu-q35-4.0 machine type should not be used in vfio-pci > configurations for devices requiring legacy INTx support without > explicitly modifying the VM configuration to use kernel irqchip. > > Link: https://bugs.launchpad.net/qemu/+bug/1826422 > Fixes: b2fc91db8447 ("q35: set split kernel irqchip as default") > Cc: qemu-stable@nongnu.org > Reviewed-by: Peter Xu > Signed-off-by: Alex Williamson Reviewed-by: Michael S. Tsirkin > --- > > Same code as v1, just updating the commit log as a formal backport of > the merged 4.1 commit. > > hw/core/machine.c | 3 +++ > hw/i386/pc.c | 3 +++ > hw/i386/pc_q35.c | 16 ++++++++++++++-- > include/hw/boards.h | 3 +++ > include/hw/i386/pc.h | 3 +++ > 5 files changed, 26 insertions(+), 2 deletions(-) > > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 743fef28982c..5d046a43e3d2 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -24,6 +24,9 @@ > #include "hw/pci/pci.h" > #include "hw/mem/nvdimm.h" > > +GlobalProperty hw_compat_4_0[] = {}; > +const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); > + > GlobalProperty hw_compat_3_1[] = { > { "pcie-root-port", "x-speed", "2_5" }, > { "pcie-root-port", "x-width", "1" }, > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index f2c15bf1f2c3..d98b737b8f3b 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -115,6 +115,9 @@ struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; > /* Physical Address of PVH entry point read from kernel ELF NOTE */ > static size_t pvh_start_addr; > > +GlobalProperty pc_compat_4_0[] = {}; > +const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); > + > GlobalProperty pc_compat_3_1[] = { > { "intel-iommu", "dma-drain", "off" }, > { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index 372c6b73bebd..45cc29d1adb7 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -357,7 +357,7 @@ static void pc_q35_machine_options(MachineClass *m) > m->units_per_default_bus = 1; > m->default_machine_opts = "firmware=bios-256k.bin"; > m->default_display = "std"; > - m->default_kernel_irqchip_split = true; > + m->default_kernel_irqchip_split = false; > m->no_floppy = 1; > machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); > machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); > @@ -365,12 +365,24 @@ static void pc_q35_machine_options(MachineClass *m) > m->max_cpus = 288; > } > > -static void pc_q35_4_0_machine_options(MachineClass *m) > +static void pc_q35_4_0_1_machine_options(MachineClass *m) > { > pc_q35_machine_options(m); > m->alias = "q35"; > } > > +DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, > + pc_q35_4_0_1_machine_options); > + > +static void pc_q35_4_0_machine_options(MachineClass *m) > +{ > + pc_q35_4_0_1_machine_options(m); > + m->default_kernel_irqchip_split = true; > + m->alias = NULL; > + compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); > + compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); > +} > + > DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, > pc_q35_4_0_machine_options); > > diff --git a/include/hw/boards.h b/include/hw/boards.h > index e231860666a1..fe1885cbffa0 100644 > --- a/include/hw/boards.h > +++ b/include/hw/boards.h > @@ -293,6 +293,9 @@ struct MachineState { > } \ > type_init(machine_initfn##_register_types) > > +extern GlobalProperty hw_compat_4_0[]; > +extern const size_t hw_compat_4_0_len; > + > extern GlobalProperty hw_compat_3_1[]; > extern const size_t hw_compat_3_1_len; > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index ca65ef18afb4..43df7230a22b 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -293,6 +293,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); > int e820_get_num_entries(void); > bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); > > +extern GlobalProperty pc_compat_4_0[]; > +extern const size_t pc_compat_4_0_len; > + > extern GlobalProperty pc_compat_3_1[]; > extern const size_t pc_compat_3_1_len; >