From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB2EC28CC5 for ; Wed, 5 Jun 2019 12:19:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9469B206BA for ; Wed, 5 Jun 2019 12:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727408AbfFEMTF (ORCPT ); Wed, 5 Jun 2019 08:19:05 -0400 Received: from foss.arm.com ([217.140.101.70]:58854 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbfFEMTF (ORCPT ); Wed, 5 Jun 2019 08:19:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 993C180D; Wed, 5 Jun 2019 05:19:04 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC1EB3F246; Wed, 5 Jun 2019 05:19:02 -0700 (PDT) Date: Wed, 5 Jun 2019 13:19:00 +0100 From: Will Deacon To: Marc Gonzalez , joro@8bytes.org Cc: Robin Murphy , MSM , Linux ARM , iommu , AngeloGioacchino Del Regno , Jeffrey Hugo , Andy Gross , Bjorn Andersson Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> References: <20190529130559.GB11023@fuggles.cambridge.arm.com> <84791515-e0ae-0322-78aa-02ca0b40d157@free.fr> <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org [+Joerg on To:] On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote: > From: Robin Murphy > > Apparently, some Qualcomm arm64 platforms which appear to expose their > SMMU global register space are still, in fact, using a hypervisor to > mediate it by trapping and emulating register accesses. Sadly, some > deployed versions of said trapping code have bugs wherein they go > horribly wrong for stores using r31 (i.e. XZR/WZR) as the source > register. > > While this can be mitigated for GCC today by tweaking the constraints > for the implementation of writel_relaxed(), to avoid any potential > arms race with future compilers more aggressively optimising register > allocation, the simple way is to just remove all the problematic > constant zeros. For the write-only TLB operations, the actual value is > irrelevant anyway and any old nearby variable will provide a suitable > GPR to encode. The one point at which we really do need a zero to clear > a context bank happens before any of the TLB maintenance where crashes > have been reported, so is apparently not a problem... :/ > > Reported-by: AngeloGioacchino Del Regno > Tested-by: Marc Gonzalez > Signed-off-by: Robin Murphy > Signed-off-by: Marc Gonzalez Acked-by: Will Deacon Joerg -- Please can you take this as a fix for 5.2, with a Cc stable? Cheers, Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E542C28CC5 for ; Wed, 5 Jun 2019 12:19:07 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2658C206BA for ; Wed, 5 Jun 2019 12:19:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2658C206BA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id DB9F3B50; Wed, 5 Jun 2019 12:19:06 +0000 (UTC) Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 58E4E9BA for ; Wed, 5 Jun 2019 12:19:05 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id EE5B634F for ; Wed, 5 Jun 2019 12:19:04 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 993C180D; Wed, 5 Jun 2019 05:19:04 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC1EB3F246; Wed, 5 Jun 2019 05:19:02 -0700 (PDT) Date: Wed, 5 Jun 2019 13:19:00 +0100 From: Will Deacon To: Marc Gonzalez , joro@8bytes.org Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> References: <20190529130559.GB11023@fuggles.cambridge.arm.com> <84791515-e0ae-0322-78aa-02ca0b40d157@free.fr> <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () Cc: Jeffrey Hugo , MSM , Bjorn Andersson , iommu , Andy Gross , AngeloGioacchino Del Regno , Robin Murphy , Linux ARM X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org [+Joerg on To:] On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote: > From: Robin Murphy > > Apparently, some Qualcomm arm64 platforms which appear to expose their > SMMU global register space are still, in fact, using a hypervisor to > mediate it by trapping and emulating register accesses. Sadly, some > deployed versions of said trapping code have bugs wherein they go > horribly wrong for stores using r31 (i.e. XZR/WZR) as the source > register. > > While this can be mitigated for GCC today by tweaking the constraints > for the implementation of writel_relaxed(), to avoid any potential > arms race with future compilers more aggressively optimising register > allocation, the simple way is to just remove all the problematic > constant zeros. For the write-only TLB operations, the actual value is > irrelevant anyway and any old nearby variable will provide a suitable > GPR to encode. The one point at which we really do need a zero to clear > a context bank happens before any of the TLB maintenance where crashes > have been reported, so is apparently not a problem... :/ > > Reported-by: AngeloGioacchino Del Regno > Tested-by: Marc Gonzalez > Signed-off-by: Robin Murphy > Signed-off-by: Marc Gonzalez Acked-by: Will Deacon Joerg -- Please can you take this as a fix for 5.2, with a Cc stable? Cheers, Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 167A4C28CC5 for ; Wed, 5 Jun 2019 12:19:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E15C5206BA for ; Wed, 5 Jun 2019 12:19:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HljCuDrH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E15C5206BA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qu2V4ak/V9qPMFuHsgsfaDhD0wVjmccXosDTiYue6e4=; b=HljCuDrHuDr1rj nA7C2Eyl3iEBmI04MrWtDQOuMNdVJQOHYY1MPPvJzR/gTCNi5ZFaB1wkyL1MvoDbWmtPql4Re4/j5 cbWNUQPlr0P1ohiqZ3964dKND3f/rX3uwCYwmWrgs0biTvS4ivhopx+g3oETqpCZcWSW8tu7DJlhs 1IQEURNfHeaBLHM76zSTdXaU2OZmqBpKJlPENSSrbIj3eJZ+ibehzySmqJoNPymVCIFW6RvPN1HDo SPKTNzZDjXHMD8BOXnnU/Kf2gWoeZJuI+d22KMHldPXtqoHHmQa2bllEKQEybGos0iGCuVhv9NpIv zHAlPe2U+4u+5mQkePtQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYUsl-0005z8-83; Wed, 05 Jun 2019 12:19:07 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYUsj-0005yo-7f for linux-arm-kernel@lists.infradead.org; Wed, 05 Jun 2019 12:19:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 993C180D; Wed, 5 Jun 2019 05:19:04 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC1EB3F246; Wed, 5 Jun 2019 05:19:02 -0700 (PDT) Date: Wed, 5 Jun 2019 13:19:00 +0100 From: Will Deacon To: Marc Gonzalez , joro@8bytes.org Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> References: <20190529130559.GB11023@fuggles.cambridge.arm.com> <84791515-e0ae-0322-78aa-02ca0b40d157@free.fr> <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190605_051905_276014_8D9BF9EA X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeffrey Hugo , MSM , Bjorn Andersson , iommu , Andy Gross , AngeloGioacchino Del Regno , Robin Murphy , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org [+Joerg on To:] On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote: > From: Robin Murphy > > Apparently, some Qualcomm arm64 platforms which appear to expose their > SMMU global register space are still, in fact, using a hypervisor to > mediate it by trapping and emulating register accesses. Sadly, some > deployed versions of said trapping code have bugs wherein they go > horribly wrong for stores using r31 (i.e. XZR/WZR) as the source > register. > > While this can be mitigated for GCC today by tweaking the constraints > for the implementation of writel_relaxed(), to avoid any potential > arms race with future compilers more aggressively optimising register > allocation, the simple way is to just remove all the problematic > constant zeros. For the write-only TLB operations, the actual value is > irrelevant anyway and any old nearby variable will provide a suitable > GPR to encode. The one point at which we really do need a zero to clear > a context bank happens before any of the TLB maintenance where crashes > have been reported, so is apparently not a problem... :/ > > Reported-by: AngeloGioacchino Del Regno > Tested-by: Marc Gonzalez > Signed-off-by: Robin Murphy > Signed-off-by: Marc Gonzalez Acked-by: Will Deacon Joerg -- Please can you take this as a fix for 5.2, with a Cc stable? Cheers, Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel