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McKenney" To: David Laight Cc: Geert Uytterhoeven , Vineet Gupta , Peter Zijlstra , Will Deacon , arcml , lkml , "linux-arch@vger.kernel.org" Subject: Re: single copy atomicity for double load/stores on 32-bit systems Reply-To: paulmck@linux.ibm.com References: <2fd3a455-6267-5d21-c530-41964a4f6ce9@synopsys.com> <20190531082112.GH2623@hirez.programming.kicks-ass.net> <20190603201324.GN28207@linux.ibm.com> <20190606094340.GD28207@linux.ibm.com> <8d1666df180d4d01aaebb5d41370b338@AcuMS.aculab.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8d1666df180d4d01aaebb5d41370b338@AcuMS.aculab.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 19060621-2213-0000-0000-0000039B2E67 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011224; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01214223; UDB=6.00638248; IPR=6.00995302; MB=3.00027212; MTD=3.00000008; XFM=3.00000015; UTC=2019-06-06 21:17:40 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19060621-2214-0000-0000-00005EBF501D Message-Id: <20190606211736.GW28207@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-06-06_14:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=988 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906060143 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 06, 2019 at 04:34:52PM +0000, David Laight wrote: > From: Paul E. McKenney > > Sent: 06 June 2019 10:44 > ... > > But m68k is !SMP-only, correct? If so, the only issues would be > > interactions with interrupt handlers and the like, and doesn't current > > m68k hardware use exact interrupts? Or is it still possible to interrupt > > an m68k in the middle of an instruction like it was in the bad old days? > > Hardware interrupts were always on instruction boundaries, the > mid-instruction interrupts would only happen for page faults (etc). OK, !SMP should be fine, then. > There were SMP m68k systems (but I can't remember one). > It was important to continue from a mid-instruction trap on the > same cpu - unless you could guarantee that all the cpus had > exactly the same version of the microcode. Yuck! ;-) > In any case you could probably use the 'cmp2' instruction > for an atomic 64bit write. > OTOH setting that up was such a PITA it was always easier > to disable interrupts. Unless I am forgetting something, given that m68k is a 32-bit system, we should be OK without an atomic 64-bit write. Thanx, Paul From mboxrd@z Thu Jan 1 00:00:00 1970 From: paulmck@linux.ibm.com (Paul E. McKenney) Date: Thu, 6 Jun 2019 14:17:36 -0700 Subject: single copy atomicity for double load/stores on 32-bit systems In-Reply-To: <8d1666df180d4d01aaebb5d41370b338@AcuMS.aculab.com> References: <2fd3a455-6267-5d21-c530-41964a4f6ce9@synopsys.com> <20190531082112.GH2623@hirez.programming.kicks-ass.net> <20190603201324.GN28207@linux.ibm.com> <20190606094340.GD28207@linux.ibm.com> <8d1666df180d4d01aaebb5d41370b338@AcuMS.aculab.com> List-ID: Message-ID: <20190606211736.GW28207@linux.ibm.com> To: linux-snps-arc@lists.infradead.org On Thu, Jun 06, 2019@04:34:52PM +0000, David Laight wrote: > From: Paul E. McKenney > > Sent: 06 June 2019 10:44 > ... > > But m68k is !SMP-only, correct? If so, the only issues would be > > interactions with interrupt handlers and the like, and doesn't current > > m68k hardware use exact interrupts? Or is it still possible to interrupt > > an m68k in the middle of an instruction like it was in the bad old days? > > Hardware interrupts were always on instruction boundaries, the > mid-instruction interrupts would only happen for page faults (etc). OK, !SMP should be fine, then. > There were SMP m68k systems (but I can't remember one). > It was important to continue from a mid-instruction trap on the > same cpu - unless you could guarantee that all the cpus had > exactly the same version of the microcode. Yuck! ;-) > In any case you could probably use the 'cmp2' instruction > for an atomic 64bit write. > OTOH setting that up was such a PITA it was always easier > to disable interrupts. Unless I am forgetting something, given that m68k is a 32-bit system, we should be OK without an atomic 64-bit write. Thanx, Paul