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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id q13sm1296215lfk.65.2019.06.08.23.18.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Jun 2019 23:18:21 -0700 (PDT) Date: Sun, 9 Jun 2019 09:18:19 +0300 From: Antony Pavlov To: Paul Walmsley Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , Rob Herring Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Message-Id: <20190609091819.2d1a97c90c0b44aa9120d373@gmail.com> In-Reply-To: <20190602080500.31700-6-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> <20190602080500.31700-6-paul.walmsley@sifive.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 2 Jun 2019 01:05:00 -0700 Paul Walmsley wrote: Hi! > Add initial board data for the SiFive HiFive Unleashed A00. >=20 > Currently the data populated in this DT file describes the board > DRAM configuration and the external clock sources that supply the > PRCI. >=20 > This third version incorporates changes based on more comments from > Rob Herring . >=20 > Signed-off-by: Paul Walmsley > Signed-off-by: Paul Walmsley > Cc: Rob Herring > Cc: Mark Rutland > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: devicetree@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/riscv/boot/dts/sifive/Makefile | 2 + > .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ > 2 files changed, 69 insertions(+) > create mode 100644 arch/riscv/boot/dts/sifive/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts >=20 > diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/si= five/Makefile > new file mode 100644 > index 000000000000..baaeef9efdcb > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-y +=3D hifive-unleashed-a00.dtb > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/r= iscv/boot/dts/sifive/hifive-unleashed-a00.dts > new file mode 100644 > index 000000000000..1de4ea1577d5 > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > @@ -0,0 +1,67 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2018-2019 SiFive, Inc */ > + > +/dts-v1/; > + > +#include "fu540-c000.dtsi" You already have "/dts-v1/;" in the fu540-c000.dtsi file. You can omit it in the hifive-unleashed-a00.dts file. > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + model =3D "SiFive HiFive Unleashed A00"; > + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; > + > + chosen { > + }; > + > + cpus { > + timebase-frequency =3D ; > + }; > + > + memory@80000000 { > + device_type =3D "memory"; > + reg =3D <0x0 0x80000000 0x2 0x00000000>; > + }; > + > + soc { > + }; > + > + hfclk: hfclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <33333333>; > + clock-output-names =3D "hfclk"; > + }; > + > + rtcclk: rtcclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D ; > + clock-output-names =3D "rtcclk"; > + }; > +}; > + > +&qspi0 { > + flash@0 { > + compatible =3D "issi,is25wp256", "jedec,spi-nor"; > + reg =3D <0>; > + spi-max-frequency =3D <50000000>; > + m25p,fast-read; > + spi-tx-bus-width =3D <4>; > + spi-rx-bus-width =3D <4>; > + }; > +}; > + > +&qspi2 { > + status =3D "okay"; > + mmc@0 { > + compatible =3D "mmc-spi-slot"; > + reg =3D <0>; > + spi-max-frequency =3D <20000000>; > + voltage-ranges =3D <3300 3300>; > + disable-wp; > + }; > +}; > --=20 > 2.20.1 >=20 >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv --=20 Best regards, =A0 Antony Pavlov From mboxrd@z Thu Jan 1 00:00:00 1970 From: Antony Pavlov Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Date: Sun, 9 Jun 2019 09:18:19 +0300 Message-ID: <20190609091819.2d1a97c90c0b44aa9120d373@gmail.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> <20190602080500.31700-6-paul.walmsley@sifive.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190602080500.31700-6-paul.walmsley@sifive.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+glpr-linux-riscv=m.gmane.org@lists.infradead.org To: Paul Walmsley Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , linux-kernel@vger.kernel.org, Rob Herring , linux-riscv@lists.infradead.org List-Id: devicetree@vger.kernel.org On Sun, 2 Jun 2019 01:05:00 -0700 Paul Walmsley wrote: Hi! > Add initial board data for the SiFive HiFive Unleashed A00. > = > Currently the data populated in this DT file describes the board > DRAM configuration and the external clock sources that supply the > PRCI. > = > This third version incorporates changes based on more comments from > Rob Herring . > = > Signed-off-by: Paul Walmsley > Signed-off-by: Paul Walmsley > Cc: Rob Herring > Cc: Mark Rutland > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: devicetree@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/riscv/boot/dts/sifive/Makefile | 2 + > .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ > 2 files changed, 69 insertions(+) > create mode 100644 arch/riscv/boot/dts/sifive/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > = > diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/si= five/Makefile > new file mode 100644 > index 000000000000..baaeef9efdcb > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-y +=3D hifive-unleashed-a00.dtb > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/r= iscv/boot/dts/sifive/hifive-unleashed-a00.dts > new file mode 100644 > index 000000000000..1de4ea1577d5 > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > @@ -0,0 +1,67 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2018-2019 SiFive, Inc */ > + > +/dts-v1/; > + > +#include "fu540-c000.dtsi" You already have "/dts-v1/;" in the fu540-c000.dtsi file. You can omit it in the hifive-unleashed-a00.dts file. > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + model =3D "SiFive HiFive Unleashed A00"; > + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; > + > + chosen { > + }; > + > + cpus { > + timebase-frequency =3D ; > + }; > + > + memory@80000000 { > + device_type =3D "memory"; > + reg =3D <0x0 0x80000000 0x2 0x00000000>; > + }; > + > + soc { > + }; > + > + hfclk: hfclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <33333333>; > + clock-output-names =3D "hfclk"; > + }; > + > + rtcclk: rtcclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D ; > + clock-output-names =3D "rtcclk"; > + }; > +}; > + > +&qspi0 { > + flash@0 { > + compatible =3D "issi,is25wp256", "jedec,spi-nor"; > + reg =3D <0>; > + spi-max-frequency =3D <50000000>; > + m25p,fast-read; > + spi-tx-bus-width =3D <4>; > + spi-rx-bus-width =3D <4>; > + }; > +}; > + > +&qspi2 { > + status =3D "okay"; > + mmc@0 { > + compatible =3D "mmc-spi-slot"; > + reg =3D <0>; > + spi-max-frequency =3D <20000000>; > + voltage-ranges =3D <3300 3300>; > + disable-wp; > + }; > +}; > -- = > 2.20.1 > = > = > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- = Best regards, =A0 Antony Pavlov From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6201DC28EBD for ; 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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id q13sm1296215lfk.65.2019.06.08.23.18.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Jun 2019 23:18:21 -0700 (PDT) Date: Sun, 9 Jun 2019 09:18:19 +0300 From: Antony Pavlov To: Paul Walmsley Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Message-Id: <20190609091819.2d1a97c90c0b44aa9120d373@gmail.com> In-Reply-To: <20190602080500.31700-6-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> <20190602080500.31700-6-paul.walmsley@sifive.com> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190608_231828_193663_B96DD0DD X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , linux-kernel@vger.kernel.org, Rob Herring , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 2 Jun 2019 01:05:00 -0700 Paul Walmsley wrote: Hi! > Add initial board data for the SiFive HiFive Unleashed A00. > = > Currently the data populated in this DT file describes the board > DRAM configuration and the external clock sources that supply the > PRCI. > = > This third version incorporates changes based on more comments from > Rob Herring . > = > Signed-off-by: Paul Walmsley > Signed-off-by: Paul Walmsley > Cc: Rob Herring > Cc: Mark Rutland > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: devicetree@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/riscv/boot/dts/sifive/Makefile | 2 + > .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ > 2 files changed, 69 insertions(+) > create mode 100644 arch/riscv/boot/dts/sifive/Makefile > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > = > diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/si= five/Makefile > new file mode 100644 > index 000000000000..baaeef9efdcb > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-y +=3D hifive-unleashed-a00.dtb > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/r= iscv/boot/dts/sifive/hifive-unleashed-a00.dts > new file mode 100644 > index 000000000000..1de4ea1577d5 > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > @@ -0,0 +1,67 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2018-2019 SiFive, Inc */ > + > +/dts-v1/; > + > +#include "fu540-c000.dtsi" You already have "/dts-v1/;" in the fu540-c000.dtsi file. You can omit it in the hifive-unleashed-a00.dts file. > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + model =3D "SiFive HiFive Unleashed A00"; > + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; > + > + chosen { > + }; > + > + cpus { > + timebase-frequency =3D ; > + }; > + > + memory@80000000 { > + device_type =3D "memory"; > + reg =3D <0x0 0x80000000 0x2 0x00000000>; > + }; > + > + soc { > + }; > + > + hfclk: hfclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <33333333>; > + clock-output-names =3D "hfclk"; > + }; > + > + rtcclk: rtcclk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D ; > + clock-output-names =3D "rtcclk"; > + }; > +}; > + > +&qspi0 { > + flash@0 { > + compatible =3D "issi,is25wp256", "jedec,spi-nor"; > + reg =3D <0>; > + spi-max-frequency =3D <50000000>; > + m25p,fast-read; > + spi-tx-bus-width =3D <4>; > + spi-rx-bus-width =3D <4>; > + }; > +}; > + > +&qspi2 { > + status =3D "okay"; > + mmc@0 { > + compatible =3D "mmc-spi-slot"; > + reg =3D <0>; > + spi-max-frequency =3D <20000000>; > + voltage-ranges =3D <3300 3300>; > + disable-wp; > + }; > +}; > -- = > 2.20.1 > = > = > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- = Best regards, =A0 Antony Pavlov _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv