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[100.0.197.103]) by smtp.gmail.com with ESMTPSA id j26sm7705325qtj.70.2019.06.11.05.06.37 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 11 Jun 2019 05:06:38 -0700 (PDT) Date: Tue, 11 Jun 2019 08:06:36 -0400 From: "Michael S. Tsirkin" To: Paolo Bonzini Message-ID: <20190611080542-mutt-send-email-mst@kernel.org> References: <20190607073429.3436-1-kraxel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.222.196 Subject: Re: [Qemu-devel] [PATCH v2] q35: fix mmconfig and PCI0._CRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "open list:All patches CC here" , Gerd Hoffmann , Igor Mammedov , =?iso-8859-1?B?TOFzemzzIMlyc2Vr?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jun 11, 2019 at 01:37:35PM +0200, Paolo Bonzini wrote: > On 07/06/19 09:34, Gerd Hoffmann wrote: > > This patch changes the handling of the mmconfig area. Thanks to the > > pci(e) expander devices we already have the logic to exclude address > > ranges from PCI0._CRS. We can simply add the mmconfig address range > > to the list get it excluded as well. > > > > With that in place we can go with a fixed pci hole which covers the > > whole area from the end of (low) ram to the ioapic. > > > > This will make the whole logic alot less fragile. No matter where the > > firmware places the mmconfig xbar, things should work correctly. The > > guest also gets a bit more PCI address space (seabios boot): > > > > # cat /proc/iomem > > [ ... ] > > 7ffdd000-7fffffff : reserved > > 80000000-afffffff : PCI Bus 0000:00 <<-- this is new > > b0000000-bfffffff : PCI MMCONFIG 0000 [bus 00-ff] > > b0000000-bfffffff : reserved > > c0000000-febfffff : PCI Bus 0000:00 > > f8000000-fbffffff : 0000:00:01.0 > > [ ... ] > > > > So this is a guest visible change. > > > > Cc: László Érsek > > Signed-off-by: Gerd Hoffmann > > Reviewed-by: Igor Mammedov > > --- > > tests/bios-tables-test-allowed-diff.h | 8 +++++++ > > hw/i386/acpi-build.c | 14 ++++++++++++ > > hw/pci-host/q35.c | 31 +++++++-------------------- > > 3 files changed, 30 insertions(+), 23 deletions(-) > > > > diff --git a/tests/bios-tables-test-allowed-diff.h b/tests/bios-tables-test-allowed-diff.h > > index dfb8523c8bf4..3bbd22c62a3b 100644 > > --- a/tests/bios-tables-test-allowed-diff.h > > +++ b/tests/bios-tables-test-allowed-diff.h > > @@ -1 +1,9 @@ > > /* List of comma-separated changed AML files to ignore */ > > +"tests/data/acpi/q35/DSDT", > > +"tests/data/acpi/q35/DSDT.bridge", > > +"tests/data/acpi/q35/DSDT.mmio64", > > +"tests/data/acpi/q35/DSDT.ipmibt", > > +"tests/data/acpi/q35/DSDT.cphp", > > +"tests/data/acpi/q35/DSDT.memhp", > > +"tests/data/acpi/q35/DSDT.numamem", > > +"tests/data/acpi/q35/DSDT.dimmpxm", > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index 85dc1640bc67..8e4f26977619 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -122,6 +122,8 @@ typedef struct FwCfgTPMConfig { > > uint8_t tpmppi_version; > > } QEMU_PACKED FwCfgTPMConfig; > > > > +static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); > > + > > static void init_common_fadt_data(Object *o, AcpiFadtData *data) > > { > > uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); > > @@ -1807,6 +1809,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > CrsRangeSet crs_range_set; > > PCMachineState *pcms = PC_MACHINE(machine); > > PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); > > + AcpiMcfgInfo mcfg; > > uint32_t nr_mem = machine->ram_slots; > > int root_bus_limit = 0xFF; > > PCIBus *bus = NULL; > > @@ -1921,6 +1924,17 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > } > > } > > > > + /* > > + * At this point crs_range_set has all the ranges used by pci > > + * busses *other* than PCI0. These ranges will be excluded from > > + * the PCI0._CRS. Add mmconfig to the set so it will be excluded > > + * too. > > + */ > > + if (acpi_get_mcfg(&mcfg)) { > > + crs_range_insert(crs_range_set.mem_ranges, > > + mcfg.base, mcfg.base + mcfg.size - 1); > > + } > > + > > scope = aml_scope("\\_SB.PCI0"); > > /* build PCI0._CRS */ > > crs = aml_resource_template(); > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > > index 960939f5ed3e..72093320befe 100644 > > --- a/hw/pci-host/q35.c > > +++ b/hw/pci-host/q35.c > > @@ -258,15 +258,6 @@ static void q35_host_initfn(Object *obj) > > object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, > > (Object **) &s->mch.address_space_io, > > qdev_prop_allow_set_link_before_realize, 0, NULL); > > - > > - /* Leave enough space for the biggest MCFG BAR */ > > - /* TODO: this matches current bios behaviour, but > > - * it's not a power of two, which means an MTRR > > - * can't cover it exactly. > > - */ > > - range_set_bounds(&s->mch.pci_hole, > > - MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, > > - IO_APIC_DEFAULT_ADDRESS - 1); > > } > > > > static const TypeInfo q35_host_info = { > > @@ -338,20 +329,6 @@ static void mch_update_pciexbar(MCHPCIState *mch) > > } > > addr = pciexbar & addr_mask; > > pcie_host_mmcfg_update(pehb, enable, addr, length); > > - /* Leave enough space for the MCFG BAR */ > > - /* > > - * TODO: this matches current bios behaviour, but it's not a power of two, > > - * which means an MTRR can't cover it exactly. > > - */ > > - if (enable) { > > - range_set_bounds(&mch->pci_hole, > > - addr + length, > > - IO_APIC_DEFAULT_ADDRESS - 1); > > - } else { > > - range_set_bounds(&mch->pci_hole, > > - MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, > > - IO_APIC_DEFAULT_ADDRESS - 1); > > - } > > } > > > > /* PAM */ > > @@ -484,6 +461,14 @@ static void mch_update(MCHPCIState *mch) > > mch_update_pam(mch); > > mch_update_smram(mch); > > mch_update_ext_tseg_mbytes(mch); > > + > > + /* > > + * pci hole goes from end-of-low-ram to io-apic. > > + * mmconfig will be excluded by the dsdt builder. > > + */ > > + range_set_bounds(&mch->pci_hole, > > + mch->below_4g_mem_size, > > + IO_APIC_DEFAULT_ADDRESS - 1); > > } > > > > static int mch_post_load(void *opaque, int version_id) > > > > Queued, thanks. > > Paolo Paolo I would prefer to queue ACPI changes through my tree. In particular there's a dance with expected tables I am still working out. -- MST