From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Subject: [PATCH 27/92] ram: rk3399: Add DdrMode Date: Tue, 11 Jun 2019 20:20:30 +0530 Message-ID: <20190611145135.21399-28-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190611145135.21399-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Jagan Teki , gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: linux-rockchip.vger.kernel.org Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki --- .../include/asm/arch-rockchip/sdram_rk3399.h | 17 ++++++++++++++++- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 924eeb3bac..a191d242f8 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -36,6 +36,21 @@ union noc_ddrtimingc0 { } b; }; +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + struct rk3399_msch_regs { u32 coreid; u32 revisionid; @@ -56,7 +71,7 @@ struct rk3399_msch_timings { u32 ddrtimingb0; union noc_ddrtimingc0 ddrtimingc0; u32 devtodev0; - u32 ddrmode; + union noc_ddrmode ddrmode; u32 agingx0; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index f9fec14758..6bf8dce6e0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1047,7 +1047,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrtimingc0); writel(noc_timing->devtodev0, &ddr_msch_regs->devtodev0); - writel(noc_timing->ddrmode, + writel(noc_timing->ddrmode.d32, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ -- 2.18.0.321.gffc6fa0e3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Tue, 11 Jun 2019 20:20:30 +0530 Subject: [U-Boot] [PATCH 27/92] ram: rk3399: Add DdrMode In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Message-ID: <20190611145135.21399-28-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki --- .../include/asm/arch-rockchip/sdram_rk3399.h | 17 ++++++++++++++++- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 924eeb3bac..a191d242f8 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -36,6 +36,21 @@ union noc_ddrtimingc0 { } b; }; +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + struct rk3399_msch_regs { u32 coreid; u32 revisionid; @@ -56,7 +71,7 @@ struct rk3399_msch_timings { u32 ddrtimingb0; union noc_ddrtimingc0 ddrtimingc0; u32 devtodev0; - u32 ddrmode; + union noc_ddrmode ddrmode; u32 agingx0; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index f9fec14758..6bf8dce6e0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1047,7 +1047,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrtimingc0); writel(noc_timing->devtodev0, &ddr_msch_regs->devtodev0); - writel(noc_timing->ddrmode, + writel(noc_timing->ddrmode.d32, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ -- 2.18.0.321.gffc6fa0e3