From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Subject: [PATCH 63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 Date: Tue, 11 Jun 2019 20:21:06 +0530 Message-ID: <20190611145135.21399-64-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190611145135.21399-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Jagan Teki , gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: linux-rockchip.vger.kernel.org PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4. So, configure the same in pctl_cfg for LPDDR4. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1abeee7198..7d2359740c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -579,6 +579,13 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); + if (sdram_params->base.dramtype == LPDDR4) { + writel(sdram_params->phy_regs.denali_phy[898], + &denali_phy[898]); + writel(sdram_params->phy_regs.denali_phy[919], + &denali_phy[919]); + } + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); -- 2.18.0.321.gffc6fa0e3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Tue, 11 Jun 2019 20:21:06 +0530 Subject: [U-Boot] [PATCH 63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Message-ID: <20190611145135.21399-64-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4. So, configure the same in pctl_cfg for LPDDR4. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1abeee7198..7d2359740c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -579,6 +579,13 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); + if (sdram_params->base.dramtype == LPDDR4) { + writel(sdram_params->phy_regs.denali_phy[898], + &denali_phy[898]); + writel(sdram_params->phy_regs.denali_phy[919], + &denali_phy[919]); + } + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); -- 2.18.0.321.gffc6fa0e3